Struct esp32s3::lcd_cam::cam_ctrl::R

pub struct R(_);

Register CAM_CTRL reader

Implementations

impl R

pub fn cam_stop_en(&self) -> CAM_STOP_EN_R

Bit 0 - Camera stop enable signal, 1: camera stops when DMA Rx FIFO is full. 0: Not stop.

pub fn cam_vsync_filter_thres(&self) -> CAM_VSYNC_FILTER_THRES_R

Bits 1:3 - Filter threshold value for CAM_VSYNC signal.

pub fn cam_update(&self) -> CAM_UPDATE_R

Bit 4 - 1: Update Camera registers, will be cleared by hardware. 0 : Not care.

pub fn cam_byte_order(&self) -> CAM_BYTE_ORDER_R

Bit 5 - 1: Change data bit order, change CAM_DATA_in[7:0] to CAM_DATA_in[0:7] in one byte mode, and bits[15:0] to bits[0:15] in two byte mode. 0: Not change.

pub fn cam_bit_order(&self) -> CAM_BIT_ORDER_R

Bit 6 - 1: invert data byte order, only valid in 2 byte mode. 0: Not change.

pub fn cam_line_int_en(&self) -> CAM_LINE_INT_EN_R

Bit 7 - 1: Enable to generate CAM_HS_INT. 0: Disable.

pub fn cam_vs_eof_en(&self) -> CAM_VS_EOF_EN_R

Bit 8 - 1: CAM_VSYNC to generate in_suc_eof. 0: in_suc_eof is controlled by reg_cam_rec_data_cyclelen.

pub fn cam_clkm_div_num(&self) -> CAM_CLKM_DIV_NUM_R

Bits 9:16 - Integral Camera clock divider value

pub fn cam_clkm_div_b(&self) -> CAM_CLKM_DIV_B_R

Bits 17:22 - Fractional clock divider numerator value

pub fn cam_clkm_div_a(&self) -> CAM_CLKM_DIV_A_R

Bits 23:28 - Fractional clock divider denominator value

pub fn cam_clk_sel(&self) -> CAM_CLK_SEL_R

Bits 29:30 - Select Camera module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: no clock.

Methods from Deref<Target = R<CAM_CTRL_SPEC>>

pub fn bits(&self) -> REG::Ux

Reads raw bits from register.

Trait Implementations

impl Deref for R

type Target = R<CAM_CTRL_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &Self::Target

Dereferences the value.

impl From<R<CAM_CTRL_SPEC>> for R

fn from(reader: R<CAM_CTRL_SPEC>) -> Self

Converts to this type from the input type.