Module esp32s3::i2s1::tx_conf

I2S TX configure register

Structs

• R
  Register TX_CONF reader
• TX_CONF_SPEC
  I2S TX configure register
• W
  Register TX_CONF writer

Type Definitions

• SIG_LOOPBACK_R
  Field SIG_LOOPBACK reader - Enable signal loop back mode with transmitter module and receiver module sharing the same WS and BCK signals.
• SIG_LOOPBACK_W
  Field SIG_LOOPBACK writer - Enable signal loop back mode with transmitter module and receiver module sharing the same WS and BCK signals.
• TX_24_FILL_EN_R
  Field TX_24_FILL_EN reader - 1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode
• TX_24_FILL_EN_W
  Field TX_24_FILL_EN writer - 1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode
• TX_BIG_ENDIAN_R
  Field TX_BIG_ENDIAN reader - I2S Tx byte endian, 1: low addr value to high addr. 0: low addr with low addr value.
• TX_BIG_ENDIAN_W
  Field TX_BIG_ENDIAN writer - I2S Tx byte endian, 1: low addr value to high addr. 0: low addr with low addr value.
• TX_BIT_ORDER_R
  Field TX_BIT_ORDER reader - I2S Tx bit endian. 1:small endian, the LSB is sent first. 0:big endian, the MSB is sent first.
• TX_BIT_ORDER_W
  Field TX_BIT_ORDER writer - I2S Tx bit endian. 1:small endian, the LSB is sent first. 0:big endian, the MSB is sent first.
• TX_CHAN_EQUAL_R
  Field TX_CHAN_EQUAL reader - 1: The value of Left channel data is equal to the value of right channel data in I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is reg_i2s_single_data in I2S TX mono mode or TDM channel select mode.
• TX_CHAN_EQUAL_W
  Field TX_CHAN_EQUAL writer - 1: The value of Left channel data is equal to the value of right channel data in I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is reg_i2s_single_data in I2S TX mono mode or TDM channel select mode.
• TX_CHAN_MOD_R
  Field TX_CHAN_MOD reader - I2S transmitter channel mode configuration bits.
• TX_CHAN_MOD_W
  Field TX_CHAN_MOD writer - I2S transmitter channel mode configuration bits.
• TX_FIFO_RESET_W
  Field TX_FIFO_RESET writer - Set this bit to reset Tx AFIFO
• TX_LEFT_ALIGN_R
  Field TX_LEFT_ALIGN reader - 1: I2S TX left alignment mode. 0: I2S TX right alignment mode.
• TX_LEFT_ALIGN_W
  Field TX_LEFT_ALIGN writer - 1: I2S TX left alignment mode. 0: I2S TX right alignment mode.
• TX_MONO_FST_VLD_R
  Field TX_MONO_FST_VLD reader - 1: The first channel data value is valid in I2S TX mono mode. 0: The second channel data value is valid in I2S TX mono mode.
• TX_MONO_FST_VLD_W
  Field TX_MONO_FST_VLD writer - 1: The first channel data value is valid in I2S TX mono mode. 0: The second channel data value is valid in I2S TX mono mode.
• TX_MONO_R
  Field TX_MONO reader - Set this bit to enable transmitter in mono mode
• TX_MONO_W
  Field TX_MONO writer - Set this bit to enable transmitter in mono mode
• TX_PCM_BYPASS_R
  Field TX_PCM_BYPASS reader - Set this bit to bypass Compress/Decompress module for transmitted data.
• TX_PCM_BYPASS_W
  Field TX_PCM_BYPASS writer - Set this bit to bypass Compress/Decompress module for transmitted data.
• TX_PCM_CONF_R
  Field TX_PCM_CONF reader - I2S TX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &
• TX_PCM_CONF_W
  Field TX_PCM_CONF writer - I2S TX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &
• TX_PDM_EN_R
  Field TX_PDM_EN reader - 1: Enable I2S PDM Tx mode . 0: Disable.
• TX_PDM_EN_W
  Field TX_PDM_EN writer - 1: Enable I2S PDM Tx mode . 0: Disable.
• TX_RESET_W
  Field TX_RESET writer - Set this bit to reset transmitter
• TX_SLAVE_MOD_R
  Field TX_SLAVE_MOD reader - Set this bit to enable slave transmitter mode
• TX_SLAVE_MOD_W
  Field TX_SLAVE_MOD writer - Set this bit to enable slave transmitter mode
• TX_START_R
  Field TX_START reader - Set this bit to start transmitting data
• TX_START_W
  Field TX_START writer - Set this bit to start transmitting data
• TX_STOP_EN_R
  Field TX_STOP_EN reader - Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emtpy
• TX_STOP_EN_W
  Field TX_STOP_EN writer - Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emtpy
• TX_TDM_EN_R
  Field TX_TDM_EN reader - 1: Enable I2S TDM Tx mode . 0: Disable.
• TX_TDM_EN_W
  Field TX_TDM_EN writer - 1: Enable I2S TDM Tx mode . 0: Disable.
• TX_UPDATE_R
  Field TX_UPDATE reader - Set 1 to update I2S TX registers from APB clock domain to I2S TX clock domain. This bit will be cleared by hardware after update register done.
• TX_UPDATE_W
  Field TX_UPDATE writer - Set 1 to update I2S TX registers from APB clock domain to I2S TX clock domain. This bit will be cleared by hardware after update register done.
• TX_WS_IDLE_POL_R
  Field TX_WS_IDLE_POL reader - 0: WS should be 0 when sending left channel data, and WS is 1in right channel. 1: WS should be 1 when sending left channel data, and WS is 0in right channel.
• TX_WS_IDLE_POL_W
  Field TX_WS_IDLE_POL writer - 0: WS should be 0 when sending left channel data, and WS is 1in right channel. 1: WS should be 1 when sending left channel data, and WS is 0in right channel.