Struct esp32s3::uhci0::RegisterBlock

source · 
#[repr(C)]
pub struct RegisterBlock {
Show 34 fields
    pub conf0: CONF0,
    pub int_raw: INT_RAW,
    pub int_st: INT_ST,
    pub int_ena: INT_ENA,
    pub int_clr: INT_CLR,
    pub app_int_set: APP_INT_SET,
    pub conf1: CONF1,
    pub state0: STATE0,
    pub state1: STATE1,
    pub escape_conf: ESCAPE_CONF,
    pub hung_conf: HUNG_CONF,
    pub ack_num: ACK_NUM,
    pub rx_head: RX_HEAD,
    pub quick_sent: QUICK_SENT,
    pub reg_q0_word0: REG_Q0_WORD0,
    pub reg_q0_word1: REG_Q0_WORD1,
    pub reg_q1_word0: REG_Q1_WORD0,
    pub reg_q1_word1: REG_Q1_WORD1,
    pub reg_q2_word0: REG_Q2_WORD0,
    pub reg_q2_word1: REG_Q2_WORD1,
    pub reg_q3_word0: REG_Q3_WORD0,
    pub reg_q3_word1: REG_Q3_WORD1,
    pub reg_q4_word0: REG_Q4_WORD0,
    pub reg_q4_word1: REG_Q4_WORD1,
    pub reg_q5_word0: REG_Q5_WORD0,
    pub reg_q5_word1: REG_Q5_WORD1,
    pub reg_q6_word0: REG_Q6_WORD0,
    pub reg_q6_word1: REG_Q6_WORD1,
    pub esc_conf0: ESC_CONF0,
    pub esc_conf1: ESC_CONF1,
    pub esc_conf2: ESC_CONF2,
    pub esc_conf3: ESC_CONF3,
    pub pkt_thres: PKT_THRES,
    pub date: DATE,

}
Expand description

Register block

Fields§

§conf0: CONF0

0x00 - UHCI configuration register

§int_raw: INT_RAW

0x04 - Raw interrupt status

§int_st: INT_ST

0x08 - Masked interrupt status

§int_ena: INT_ENA

0x0c - Interrupt enable bits

§int_clr: INT_CLR

0x10 - Interrupt clear bits

§app_int_set: APP_INT_SET

0x14 - Software interrupt trigger source

§conf1: CONF1

0x18 - UHCI configuration register

§state0: STATE0

0x1c - UHCI receive status

§state1: STATE1

0x20 - UHCI transmit status

§escape_conf: ESCAPE_CONF

0x24 - Escape character configuration

§hung_conf: HUNG_CONF

0x28 - Timeout configuration

§ack_num: ACK_NUM

0x2c - UHCI ACK number configuration

§rx_head: RX_HEAD

0x30 - UHCI packet header register

§quick_sent: QUICK_SENT

0x34 - UHCI quick send configuration register

§reg_q0_word0: REG_Q0_WORD0

0x38 - Q0_WORD0 quick_sent register

§reg_q0_word1: REG_Q0_WORD1

0x3c - Q0_WORD1 quick_sent register

§reg_q1_word0: REG_Q1_WORD0

0x40 - Q1_WORD0 quick_sent register

§reg_q1_word1: REG_Q1_WORD1

0x44 - Q1_WORD1 quick_sent register

§reg_q2_word0: REG_Q2_WORD0

0x48 - Q2_WORD0 quick_sent register

§reg_q2_word1: REG_Q2_WORD1

0x4c - Q2_WORD1 quick_sent register

§reg_q3_word0: REG_Q3_WORD0

0x50 - Q3_WORD0 quick_sent register

§reg_q3_word1: REG_Q3_WORD1

0x54 - Q3_WORD1 quick_sent register

§reg_q4_word0: REG_Q4_WORD0

0x58 - Q4_WORD0 quick_sent register

§reg_q4_word1: REG_Q4_WORD1

0x5c - Q4_WORD1 quick_sent register

§reg_q5_word0: REG_Q5_WORD0

0x60 - Q5_WORD0 quick_sent register

§reg_q5_word1: REG_Q5_WORD1

0x64 - Q5_WORD1 quick_sent register

§reg_q6_word0: REG_Q6_WORD0

0x68 - Q6_WORD0 quick_sent register

§reg_q6_word1: REG_Q6_WORD1

0x6c - Q6_WORD1 quick_sent register

§esc_conf0: ESC_CONF0

0x70 - Escape sequence configuration register 0

§esc_conf1: ESC_CONF1

0x74 - Escape sequence configuration register 1

§esc_conf2: ESC_CONF2

0x78 - Escape sequence configuration register 2

§esc_conf3: ESC_CONF3

0x7c - Escape sequence configuration register 3

§pkt_thres: PKT_THRES

0x80 - Configure register for packet length

§date: DATE

0x84 - UHCI version control register

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