Struct esp32s3::spi1::cmd::R

pub struct R(_);

Register CMD reader

Implementations

impl R

pub fn flash_pe(&self) -> FLASH_PE_R

Bit 17 - In user mode, it is set to indicate that program/erase operation will be triggered. The bit is combined with SPI_MEM_USR bit. The bit will be cleared once the operation done.1: enable 0: disable.

pub fn usr(&self) -> USR_R

Bit 18 - User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.

pub fn flash_hpm(&self) -> FLASH_HPM_R

Bit 19 - Drive Flash into high performance mode. The bit will be cleared once the operation done.1: enable 0: disable.

pub fn flash_res(&self) -> FLASH_RES_R

Bit 20 - This bit combined with SPI_MEM_RESANDRES bit releases Flash from the power-down state or high performance mode and obtains the devices ID. The bit will be cleared once the operation done.1: enable 0: disable.

pub fn flash_dp(&self) -> FLASH_DP_R

Bit 21 - Drive Flash into power down. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.

pub fn flash_ce(&self) -> FLASH_CE_R

Bit 22 - Chip erase enable. Chip erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.

pub fn flash_be(&self) -> FLASH_BE_R

Bit 23 - Block erase enable(32KB) . Block erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.

pub fn flash_se(&self) -> FLASH_SE_R

Bit 24 - Sector erase enable(4KB). Sector erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.

pub fn flash_pp(&self) -> FLASH_PP_R

Bit 25 - Page program enable(1 byte ~64 bytes data to be programmed). Page program operation will be triggered when the bit is set. The bit will be cleared once the operation done .1: enable 0: disable.

pub fn flash_wrsr(&self) -> FLASH_WRSR_R

Bit 26 - Write status register enable. Write status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.

pub fn flash_rdsr(&self) -> FLASH_RDSR_R

Bit 27 - Read status register-1. Read status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.

pub fn flash_rdid(&self) -> FLASH_RDID_R

Bit 28 - Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.

pub fn flash_wrdi(&self) -> FLASH_WRDI_R

Bit 29 - Write flash disable. Write disable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.

pub fn flash_wren(&self) -> FLASH_WREN_R

Bit 30 - Write flash enable. Write enable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.

pub fn flash_read(&self) -> FLASH_READ_R

Bit 31 - Read flash enable. Read flash operation will be triggered when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.

Methods from Deref<Target = R<CMD_SPEC>>

pub fn bits(&self) -> REG::Ux

Reads raw bits from register.

Trait Implementations

impl Deref for R

type Target = R<CMD_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &Self::Target

Dereferences the value.

impl From<R<CMD_SPEC>> for R

fn from(reader: R<CMD_SPEC>) -> Self

Converts to this type from the input type.