Struct esp32s3::spi0::sram_cmd::R

pub struct R(_);

Register SRAM_CMD reader

Implementations

impl R

pub fn sclk_mode(&self) -> SCLK_MODE_R

Bits 0:1 - SPI_CLK mode bits when SPI0 accesses to Ext_RAM. 0: SPI_CLK is off when CS inactive 1: SPI_CLK is delayed one cycle after CS inactive 2: SPI_CLK is delayed two cycles after CS inactive 3: SPI_CLK is always on.

pub fn swb_mode(&self) -> SWB_MODE_R

Bits 2:9 - Mode bits when SPI0 accesses to Ext_RAM.

pub fn sdin_dual(&self) -> SDIN_DUAL_R

Bit 10 - When SPI0 accesses to Ext_RAM, set this bit to enable 2-bm in DIN phase.

pub fn sdout_dual(&self) -> SDOUT_DUAL_R

Bit 11 - When SPI0 accesses to Ext_RAM, set this bit to enable 2-bm in DOUT phase.

pub fn saddr_dual(&self) -> SADDR_DUAL_R

Bit 12 - When SPI0 accesses to Ext_RAM, set this bit to enable 2-bm in ADDR phase.

pub fn scmd_dual(&self) -> SCMD_DUAL_R

Bit 13 - When SPI0 accesses to Ext_RAM, set this bit to enable 2-bm in CMD phase.

pub fn sdin_quad(&self) -> SDIN_QUAD_R

Bit 14 - When SPI0 accesses to Ext_RAM, set this bit to enable 4-bm in DIN phase.

pub fn sdout_quad(&self) -> SDOUT_QUAD_R

Bit 15 - When SPI0 accesses to Ext_RAM, set this bit to enable 4-bm in DOUT phase.

pub fn saddr_quad(&self) -> SADDR_QUAD_R

Bit 16 - When SPI0 accesses to Ext_RAM, set this bit to enable 4-bm in ADDR phase.

pub fn scmd_quad(&self) -> SCMD_QUAD_R

Bit 17 - When SPI0 accesses to Ext_RAM, set this bit to enable 4-bm in CMD phase.

pub fn sdin_oct(&self) -> SDIN_OCT_R

Bit 18 - When SPI0 accesses to Ext_RAM, set this bit to enable 8-bm in DIN phase.

pub fn sdout_oct(&self) -> SDOUT_OCT_R

Bit 19 - When SPI0 accesses to Ext_RAM, set this bit to enable 8-bm in DOUT phase.

pub fn saddr_oct(&self) -> SADDR_OCT_R

Bit 20 - When SPI0 accesses to Ext_RAM, set this bit to enable 8-bm in ADDR phase.

pub fn scmd_oct(&self) -> SCMD_OCT_R

Bit 21 - When SPI0 accesses to Ext_RAM, set this bit to enable 8-bm in CMD phase.

pub fn sdummy_out(&self) -> SDUMMY_OUT_R

Bit 22 - When SPI0 accesses to Ext_RAM, in the DUMMY phase the signal level of SPI bus is output by the SPI0 controller.

Methods from Deref<Target = R<SRAM_CMD_SPEC>>

pub fn bits(&self) -> REG::Ux

Reads raw bits from register.

Trait Implementations

impl Deref for R

type Target = R<SRAM_CMD_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &Self::Target

Dereferences the value.

impl From<R<SRAM_CMD_SPEC>> for R

fn from(reader: R<SRAM_CMD_SPEC>) -> Self

Converts to this type from the input type.