Struct esp32s3::uart0::RegisterBlock

source · 
#[repr(C)]
pub struct RegisterBlock {
Show 33 fields
    pub fifo: FIFO,
    pub int_raw: INT_RAW,
    pub int_st: INT_ST,
    pub int_ena: INT_ENA,
    pub int_clr: INT_CLR,
    pub clkdiv: CLKDIV,
    pub rx_filt: RX_FILT,
    pub status: STATUS,
    pub conf0: CONF0,
    pub conf1: CONF1,
    pub lowpulse: LOWPULSE,
    pub highpulse: HIGHPULSE,
    pub rxd_cnt: RXD_CNT,
    pub flow_conf: FLOW_CONF,
    pub sleep_conf: SLEEP_CONF,
    pub swfc_conf0: SWFC_CONF0,
    pub swfc_conf1: SWFC_CONF1,
    pub txbrk_conf: TXBRK_CONF,
    pub idle_conf: IDLE_CONF,
    pub rs485_conf: RS485_CONF,
    pub at_cmd_precnt: AT_CMD_PRECNT,
    pub at_cmd_postcnt: AT_CMD_POSTCNT,
    pub at_cmd_gaptout: AT_CMD_GAPTOUT,
    pub at_cmd_char: AT_CMD_CHAR,
    pub mem_conf: MEM_CONF,
    pub mem_tx_status: MEM_TX_STATUS,
    pub mem_rx_status: MEM_RX_STATUS,
    pub fsm_status: FSM_STATUS,
    pub pospulse: POSPULSE,
    pub negpulse: NEGPULSE,
    pub clk_conf: CLK_CONF,
    pub date: DATE,
    pub id: ID,

}
Expand description

Register block

Fields§

§fifo: FIFO

0x00 - FIFO data register

§int_raw: INT_RAW

0x04 - Raw interrupt status

§int_st: INT_ST

0x08 - Masked interrupt status

§int_ena: INT_ENA

0x0c - Interrupt enable bits

§int_clr: INT_CLR

0x10 - Interrupt clear bits

§clkdiv: CLKDIV

0x14 - Clock divider configuration

§rx_filt: RX_FILT

0x18 - Rx Filter configuration

§status: STATUS

0x1c - UART status register

§conf0: CONF0

0x20 - a

§conf1: CONF1

0x24 - Configuration register 1

§lowpulse: LOWPULSE

0x28 - Autobaud minimum low pulse duration register

§highpulse: HIGHPULSE

0x2c - Autobaud minimum high pulse duration register

§rxd_cnt: RXD_CNT

0x30 - Autobaud edge change count register

§flow_conf: FLOW_CONF

0x34 - Software flow-control configuration

§sleep_conf: SLEEP_CONF

0x38 - Sleep-mode configuration

§swfc_conf0: SWFC_CONF0

0x3c - Software flow-control character configuration

§swfc_conf1: SWFC_CONF1

0x40 - Software flow-control character configuration

§txbrk_conf: TXBRK_CONF

0x44 - Tx Break character configuration

§idle_conf: IDLE_CONF

0x48 - Frame-end idle configuration

§rs485_conf: RS485_CONF

0x4c - RS485 mode configuration

§at_cmd_precnt: AT_CMD_PRECNT

0x50 - Pre-sequence timing configuration

§at_cmd_postcnt: AT_CMD_POSTCNT

0x54 - Post-sequence timing configuration

§at_cmd_gaptout: AT_CMD_GAPTOUT

0x58 - Timeout configuration

§at_cmd_char: AT_CMD_CHAR

0x5c - AT escape sequence detection configuration

§mem_conf: MEM_CONF

0x60 - UART threshold and allocation configuration

§mem_tx_status: MEM_TX_STATUS

0x64 - Tx-FIFO write and read offset address.

§mem_rx_status: MEM_RX_STATUS

0x68 - Rx-FIFO write and read offset address.

§fsm_status: FSM_STATUS

0x6c - UART transmit and receive status.

§pospulse: POSPULSE

0x70 - Autobaud high pulse register

§negpulse: NEGPULSE

0x74 - Autobaud low pulse register

§clk_conf: CLK_CONF

0x78 - UART core clock configuration

§date: DATE

0x7c - UART Version register

§id: ID

0x80 - UART ID register

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