Struct esp32s3::spi2::dma_int_raw::W

pub struct W(_);

Register DMA_INT_RAW writer

Implementations

impl W

pub fn dma_infifo_full_err_int_raw( &mut self ) -> DMA_INFIFO_FULL_ERR_INT_RAW_W<'_, 0>

Bit 0 - 1: The current data rate of DMA Rx is smaller than that of SPI, which will lose the receive data. 0: Others.

pub fn dma_outfifo_empty_err_int_raw( &mut self ) -> DMA_OUTFIFO_EMPTY_ERR_INT_RAW_W<'_, 1>

Bit 1 - 1: The current data rate of DMA TX is smaller than that of SPI. SPI will stop in master mode and send out all 0 in slave mode. 0: Others.

pub fn slv_ex_qpi_int_raw(&mut self) -> SLV_EX_QPI_INT_RAW_W<'_, 2>

Bit 2 - The raw bit for SPI slave Ex_QPI interrupt. 1: SPI slave mode Ex_QPI transmission is ended. 0: Others.

pub fn slv_en_qpi_int_raw(&mut self) -> SLV_EN_QPI_INT_RAW_W<'_, 3>

Bit 3 - The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode En_QPI transmission is ended. 0: Others.

pub fn slv_cmd7_int_raw(&mut self) -> SLV_CMD7_INT_RAW_W<'_, 4>

Bit 4 - The raw bit for SPI slave CMD7 interrupt. 1: SPI slave mode CMD7 transmission is ended. 0: Others.

pub fn slv_cmd8_int_raw(&mut self) -> SLV_CMD8_INT_RAW_W<'_, 5>

Bit 5 - The raw bit for SPI slave CMD8 interrupt. 1: SPI slave mode CMD8 transmission is ended. 0: Others.

pub fn slv_cmd9_int_raw(&mut self) -> SLV_CMD9_INT_RAW_W<'_, 6>

Bit 6 - The raw bit for SPI slave CMD9 interrupt. 1: SPI slave mode CMD9 transmission is ended. 0: Others.

pub fn slv_cmda_int_raw(&mut self) -> SLV_CMDA_INT_RAW_W<'_, 7>

Bit 7 - The raw bit for SPI slave CMDA interrupt. 1: SPI slave mode CMDA transmission is ended. 0: Others.

pub fn slv_rd_dma_done_int_raw(&mut self) -> SLV_RD_DMA_DONE_INT_RAW_W<'_, 8>

Bit 8 - The raw bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1: SPI slave mode Rd_DMA transmission is ended. 0: Others.

pub fn slv_wr_dma_done_int_raw(&mut self) -> SLV_WR_DMA_DONE_INT_RAW_W<'_, 9>

Bit 9 - The raw bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1: SPI slave mode Wr_DMA transmission is ended. 0: Others.

pub fn slv_rd_buf_done_int_raw(&mut self) -> SLV_RD_BUF_DONE_INT_RAW_W<'_, 10>

Bit 10 - The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave mode Rd_BUF transmission is ended. 0: Others.

pub fn slv_wr_buf_done_int_raw(&mut self) -> SLV_WR_BUF_DONE_INT_RAW_W<'_, 11>

Bit 11 - The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave mode Wr_BUF transmission is ended. 0: Others.

pub fn trans_done_int_raw(&mut self) -> TRANS_DONE_INT_RAW_W<'_, 12>

Bit 12 - The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master mode transmission is ended. 0: others.

pub fn dma_seg_trans_done_int_raw( &mut self ) -> DMA_SEG_TRANS_DONE_INT_RAW_W<'_, 13>

Bit 13 - The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1: spi master DMA full-duplex/half-duplex seg-conf-trans ends or slave half-duplex seg-trans ends. And data has been pushed to corresponding memory. 0: seg-conf-trans or seg-trans is not ended or not occurred.

pub fn seg_magic_err_int_raw(&mut self) -> SEG_MAGIC_ERR_INT_RAW_W<'_, 14>

Bit 14 - The raw bit for SPI_SEG_MAGIC_ERR_INT interrupt. 1: The magic value in CONF buffer is error in the DMA seg-conf-trans. 0: others.

pub fn slv_buf_addr_err_int_raw(&mut self) -> SLV_BUF_ADDR_ERR_INT_RAW_W<'_, 15>

Bit 15 - The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission is bigger than 63. 0: Others.

pub fn slv_cmd_err_int_raw(&mut self) -> SLV_CMD_ERR_INT_RAW_W<'_, 16>

Bit 16 - The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave command value in the current SPI slave HD mode transmission is not supported. 0: Others.

pub fn mst_rx_afifo_wfull_err_int_raw( &mut self ) -> MST_RX_AFIFO_WFULL_ERR_INT_RAW_W<'_, 17>

Bit 17 - The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: There is a RX AFIFO write-full error when SPI inputs data in master mode. 0: Others.

pub fn mst_tx_afifo_rempty_err_int_raw( &mut self ) -> MST_TX_AFIFO_REMPTY_ERR_INT_RAW_W<'_, 18>

Bit 18 - The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1: There is a TX BUF AFIFO read-empty error when SPI outputs data in master mode. 0: Others.

pub fn app2_int_raw(&mut self) -> APP2_INT_RAW_W<'_, 19>

Bit 19 - The raw bit for SPI_APP2_INT interrupt. The value is only controlled by software.

pub fn app1_int_raw(&mut self) -> APP1_INT_RAW_W<'_, 20>

Bit 20 - The raw bit for SPI_APP1_INT interrupt. The value is only controlled by software.

pub unsafe fn bits(&mut self, bits: u32) -> &mut Self

Writes raw bits to the register.

Methods from Deref<Target = W<DMA_INT_RAW_SPEC>>

pub unsafe fn bits(&mut self, bits: REG::Ux) -> &mut Self

Writes raw bits to the register.

Safety

Read datasheet or reference manual to find what values are allowed to pass.

Trait Implementations

impl Deref for W

type Target = W<DMA_INT_RAW_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &Self::Target

Dereferences the value.

impl DerefMut for W

fn deref_mut(&mut self) -> &mut Self::Target

Mutably dereferences the value.

impl From<W<DMA_INT_RAW_SPEC>> for W

fn from(writer: W<DMA_INT_RAW_SPEC>) -> Self

Converts to this type from the input type.