Struct esp32s3::interrupt_core1::cache_core1_acs_int_map::W

pub struct W(_);

Register CACHE_CORE1_ACS_INT_MAP writer

Implementations

impl W

pub fn cache_core1_acs_int_map(&mut self) -> CACHE_CORE1_ACS_INT_MAP_W<'_, 0>

Bits 0:4 - this register used to map cache_core1_acs interrupt to one of core1’s external interrupt

pub unsafe fn bits(&mut self, bits: u32) -> &mut Self

Writes raw bits to the register.

Methods from Deref<Target = W<CACHE_CORE1_ACS_INT_MAP_SPEC>>

pub unsafe fn bits(&mut self, bits: REG::Ux) -> &mut Self

Writes raw bits to the register.

Safety

Read datasheet or reference manual to find what values are allowed to pass.

Trait Implementations

impl Deref for W

type Target = W<CACHE_CORE1_ACS_INT_MAP_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &Self::Target

Dereferences the value.

impl DerefMut for W

fn deref_mut(&mut self) -> &mut Self::Target

Mutably dereferences the value.

impl From<W<CACHE_CORE1_ACS_INT_MAP_SPEC>> for W

fn from(writer: W<CACHE_CORE1_ACS_INT_MAP_SPEC>) -> Self

Converts to this type from the input type.