Struct esp32s3::dma::RegisterBlock
source · #[repr(C)]pub struct RegisterBlock {Show 200 fields
pub in_conf0_ch0: IN_CONF0_CH,
pub in_conf1_ch0: IN_CONF1_CH,
pub in_int_raw_ch0: IN_INT_RAW_CH,
pub in_int_st_ch0: IN_INT_ST_CH,
pub in_int_ena_ch0: IN_INT_ENA_CH,
pub in_int_clr_ch0: IN_INT_CLR_CH,
pub infifo_status_ch0: INFIFO_STATUS_CH,
pub in_pop_ch0: IN_POP_CH,
pub in_link_ch0: IN_LINK_CH,
pub in_state_ch0: IN_STATE_CH,
pub in_suc_eof_des_addr_ch0: IN_SUC_EOF_DES_ADDR_CH,
pub in_err_eof_des_addr_ch0: IN_ERR_EOF_DES_ADDR_CH,
pub in_dscr_ch0: IN_DSCR_CH,
pub in_dscr_bf0_ch0: IN_DSCR_BF0_CH,
pub in_dscr_bf1_ch0: IN_DSCR_BF1_CH,
pub in_wight_ch0: IN_WIGHT_CH,
pub in_pri_ch0: IN_PRI_CH,
pub in_peri_sel_ch0: IN_PERI_SEL_CH,
pub out_conf0_ch0: OUT_CONF0_CH,
pub out_conf1_ch0: OUT_CONF1_CH,
pub out_int_raw_ch0: OUT_INT_RAW_CH,
pub out_int_st_ch0: OUT_INT_ST_CH,
pub out_int_ena_ch0: OUT_INT_ENA_CH,
pub out_int_clr_ch0: OUT_INT_CLR_CH,
pub outfifo_status_ch0: OUTFIFO_STATUS_CH,
pub out_push_ch0: OUT_PUSH_CH,
pub out_link_ch0: OUT_LINK_CH,
pub out_state_ch0: OUT_STATE_CH,
pub out_eof_des_addr_ch0: OUT_EOF_DES_ADDR_CH,
pub out_eof_bfr_des_addr_ch0: OUT_EOF_BFR_DES_ADDR_CH,
pub out_dscr_ch0: OUT_DSCR_CH,
pub out_dscr_bf0_ch0: OUT_DSCR_BF0_CH,
pub out_dscr_bf1_ch0: OUT_DSCR_BF1_CH,
pub out_wight_ch0: OUT_WIGHT_CH,
pub out_pri_ch0: OUT_PRI_CH,
pub out_peri_sel_ch0: OUT_PERI_SEL_CH,
pub in_conf0_ch1: IN_CONF0_CH,
pub in_conf1_ch1: IN_CONF1_CH,
pub in_int_raw_ch1: IN_INT_RAW_CH,
pub in_int_st_ch1: IN_INT_ST_CH,
pub in_int_ena_ch1: IN_INT_ENA_CH,
pub in_int_clr_ch1: IN_INT_CLR_CH,
pub infifo_status_ch1: INFIFO_STATUS_CH,
pub in_pop_ch1: IN_POP_CH,
pub in_link_ch1: IN_LINK_CH,
pub in_state_ch1: IN_STATE_CH,
pub in_suc_eof_des_addr_ch1: IN_SUC_EOF_DES_ADDR_CH,
pub in_err_eof_des_addr_ch1: IN_ERR_EOF_DES_ADDR_CH,
pub in_dscr_ch1: IN_DSCR_CH,
pub in_dscr_bf0_ch1: IN_DSCR_BF0_CH,
pub in_dscr_bf1_ch1: IN_DSCR_BF1_CH,
pub in_wight_ch1: IN_WIGHT_CH,
pub in_pri_ch1: IN_PRI_CH,
pub in_peri_sel_ch1: IN_PERI_SEL_CH,
pub out_conf0_ch1: OUT_CONF0_CH,
pub out_conf1_ch1: OUT_CONF1_CH,
pub out_int_raw_ch1: OUT_INT_RAW_CH,
pub out_int_st_ch1: OUT_INT_ST_CH,
pub out_int_ena_ch1: OUT_INT_ENA_CH,
pub out_int_clr_ch1: OUT_INT_CLR_CH,
pub outfifo_status_ch1: OUTFIFO_STATUS_CH,
pub out_push_ch1: OUT_PUSH_CH,
pub out_link_ch1: OUT_LINK_CH,
pub out_state_ch1: OUT_STATE_CH,
pub out_eof_des_addr_ch1: OUT_EOF_DES_ADDR_CH,
pub out_eof_bfr_des_addr_ch1: OUT_EOF_BFR_DES_ADDR_CH,
pub out_dscr_ch1: OUT_DSCR_CH,
pub out_dscr_bf0_ch1: OUT_DSCR_BF0_CH,
pub out_dscr_bf1_ch1: OUT_DSCR_BF1_CH,
pub out_wight_ch1: OUT_WIGHT_CH,
pub out_pri_ch1: OUT_PRI_CH,
pub out_peri_sel_ch1: OUT_PERI_SEL_CH,
pub in_conf0_ch2: IN_CONF0_CH,
pub in_conf1_ch2: IN_CONF1_CH,
pub in_int_raw_ch2: IN_INT_RAW_CH,
pub in_int_st_ch2: IN_INT_ST_CH,
pub in_int_ena_ch2: IN_INT_ENA_CH,
pub in_int_clr_ch2: IN_INT_CLR_CH,
pub infifo_status_ch2: INFIFO_STATUS_CH,
pub in_pop_ch2: IN_POP_CH,
pub in_link_ch2: IN_LINK_CH,
pub in_state_ch2: IN_STATE_CH,
pub in_suc_eof_des_addr_ch2: IN_SUC_EOF_DES_ADDR_CH,
pub in_err_eof_des_addr_ch2: IN_ERR_EOF_DES_ADDR_CH,
pub in_dscr_ch2: IN_DSCR_CH,
pub in_dscr_bf0_ch2: IN_DSCR_BF0_CH,
pub in_dscr_bf1_ch2: IN_DSCR_BF1_CH,
pub in_wight_ch2: IN_WIGHT_CH,
pub in_pri_ch2: IN_PRI_CH,
pub in_peri_sel_ch2: IN_PERI_SEL_CH,
pub out_conf0_ch2: OUT_CONF0_CH,
pub out_conf1_ch2: OUT_CONF1_CH,
pub out_int_raw_ch2: OUT_INT_RAW_CH,
pub out_int_st_ch2: OUT_INT_ST_CH,
pub out_int_ena_ch2: OUT_INT_ENA_CH,
pub out_int_clr_ch2: OUT_INT_CLR_CH,
pub outfifo_status_ch2: OUTFIFO_STATUS_CH,
pub out_push_ch2: OUT_PUSH_CH,
pub out_link_ch2: OUT_LINK_CH,
pub out_state_ch2: OUT_STATE_CH,
pub out_eof_des_addr_ch2: OUT_EOF_DES_ADDR_CH,
pub out_eof_bfr_des_addr_ch2: OUT_EOF_BFR_DES_ADDR_CH,
pub out_dscr_ch2: OUT_DSCR_CH,
pub out_dscr_bf0_ch2: OUT_DSCR_BF0_CH,
pub out_dscr_bf1_ch2: OUT_DSCR_BF1_CH,
pub out_wight_ch2: OUT_WIGHT_CH,
pub out_pri_ch2: OUT_PRI_CH,
pub out_peri_sel_ch2: OUT_PERI_SEL_CH,
pub in_conf0_ch3: IN_CONF0_CH,
pub in_conf1_ch3: IN_CONF1_CH,
pub in_int_raw_ch3: IN_INT_RAW_CH,
pub in_int_st_ch3: IN_INT_ST_CH,
pub in_int_ena_ch3: IN_INT_ENA_CH,
pub in_int_clr_ch3: IN_INT_CLR_CH,
pub infifo_status_ch3: INFIFO_STATUS_CH,
pub in_pop_ch3: IN_POP_CH,
pub in_link_ch3: IN_LINK_CH,
pub in_state_ch3: IN_STATE_CH,
pub in_suc_eof_des_addr_ch3: IN_SUC_EOF_DES_ADDR_CH,
pub in_err_eof_des_addr_ch3: IN_ERR_EOF_DES_ADDR_CH,
pub in_dscr_ch3: IN_DSCR_CH,
pub in_dscr_bf0_ch3: IN_DSCR_BF0_CH,
pub in_dscr_bf1_ch3: IN_DSCR_BF1_CH,
pub in_wight_ch3: IN_WIGHT_CH,
pub in_pri_ch3: IN_PRI_CH,
pub in_peri_sel_ch3: IN_PERI_SEL_CH,
pub out_conf0_ch3: OUT_CONF0_CH,
pub out_conf1_ch3: OUT_CONF1_CH,
pub out_int_raw_ch3: OUT_INT_RAW_CH,
pub out_int_st_ch3: OUT_INT_ST_CH,
pub out_int_ena_ch3: OUT_INT_ENA_CH,
pub out_int_clr_ch3: OUT_INT_CLR_CH,
pub outfifo_status_ch3: OUTFIFO_STATUS_CH,
pub out_push_ch3: OUT_PUSH_CH,
pub out_link_ch3: OUT_LINK_CH,
pub out_state_ch3: OUT_STATE_CH,
pub out_eof_des_addr_ch3: OUT_EOF_DES_ADDR_CH,
pub out_eof_bfr_des_addr_ch3: OUT_EOF_BFR_DES_ADDR_CH,
pub out_dscr_ch3: OUT_DSCR_CH,
pub out_dscr_bf0_ch3: OUT_DSCR_BF0_CH,
pub out_dscr_bf1_ch3: OUT_DSCR_BF1_CH,
pub out_wight_ch3: OUT_WIGHT_CH,
pub out_pri_ch3: OUT_PRI_CH,
pub out_peri_sel_ch3: OUT_PERI_SEL_CH,
pub in_conf0_ch4: IN_CONF0_CH,
pub in_conf1_ch4: IN_CONF1_CH,
pub in_int_raw_ch4: IN_INT_RAW_CH,
pub in_int_st_ch4: IN_INT_ST_CH,
pub in_int_ena_ch4: IN_INT_ENA_CH,
pub in_int_clr_ch4: IN_INT_CLR_CH,
pub infifo_status_ch4: INFIFO_STATUS_CH,
pub in_pop_ch4: IN_POP_CH,
pub in_link_ch4: IN_LINK_CH,
pub in_state_ch4: IN_STATE_CH,
pub in_suc_eof_des_addr_ch4: IN_SUC_EOF_DES_ADDR_CH,
pub in_err_eof_des_addr_ch4: IN_ERR_EOF_DES_ADDR_CH,
pub in_dscr_ch4: IN_DSCR_CH,
pub in_dscr_bf0_ch4: IN_DSCR_BF0_CH,
pub in_dscr_bf1_ch4: IN_DSCR_BF1_CH,
pub in_wight_ch4: IN_WIGHT_CH,
pub in_pri_ch4: IN_PRI_CH,
pub in_peri_sel_ch4: IN_PERI_SEL_CH,
pub out_conf0_ch4: OUT_CONF0_CH,
pub out_conf1_ch4: OUT_CONF1_CH,
pub out_int_raw_ch4: OUT_INT_RAW_CH,
pub out_int_st_ch4: OUT_INT_ST_CH,
pub out_int_ena_ch4: OUT_INT_ENA_CH,
pub out_int_clr_ch4: OUT_INT_CLR_CH,
pub outfifo_status_ch4: OUTFIFO_STATUS_CH,
pub out_push_ch4: OUT_PUSH_CH,
pub out_link_ch4: OUT_LINK_CH,
pub out_state_ch4: OUT_STATE_CH,
pub out_eof_des_addr_ch4: OUT_EOF_DES_ADDR_CH,
pub out_eof_bfr_des_addr_ch4: OUT_EOF_BFR_DES_ADDR_CH,
pub out_dscr_ch4: OUT_DSCR_CH,
pub out_dscr_bf0_ch4: OUT_DSCR_BF0_CH,
pub out_dscr_bf1_ch4: OUT_DSCR_BF1_CH,
pub out_wight_ch4: OUT_WIGHT_CH,
pub out_pri_ch4: OUT_PRI_CH,
pub out_peri_sel_ch4: OUT_PERI_SEL_CH,
pub ahb_test: AHB_TEST,
pub pd_conf: PD_CONF,
pub misc_conf: MISC_CONF,
pub in_sram_size_ch0: IN_SRAM_SIZE_CH,
pub out_sram_size_ch0: OUT_SRAM_SIZE_CH,
pub in_sram_size_ch1: IN_SRAM_SIZE_CH,
pub out_sram_size_ch1: OUT_SRAM_SIZE_CH,
pub in_sram_size_ch2: IN_SRAM_SIZE_CH,
pub out_sram_size_ch2: OUT_SRAM_SIZE_CH,
pub in_sram_size_ch3: IN_SRAM_SIZE_CH,
pub out_sram_size_ch3: OUT_SRAM_SIZE_CH,
pub in_sram_size_ch4: IN_SRAM_SIZE_CH,
pub out_sram_size_ch4: OUT_SRAM_SIZE_CH,
pub extmem_reject_addr: EXTMEM_REJECT_ADDR,
pub extmem_reject_st: EXTMEM_REJECT_ST,
pub extmem_reject_int_raw: EXTMEM_REJECT_INT_RAW,
pub extmem_reject_int_st: EXTMEM_REJECT_INT_ST,
pub extmem_reject_int_ena: EXTMEM_REJECT_INT_ENA,
pub extmem_reject_int_clr: EXTMEM_REJECT_INT_CLR,
pub date: DATE,
/* private fields */
}Expand description
Register block
Fields§
§in_conf0_ch0: IN_CONF0_CH0x00 - Configure 0 register of Rx channel 0
in_conf1_ch0: IN_CONF1_CH0x04 - Configure 1 register of Rx channel 0
in_int_raw_ch0: IN_INT_RAW_CH0x08 - Raw status interrupt of Rx channel 0
in_int_st_ch0: IN_INT_ST_CH0x0c - Masked interrupt of Rx channel 0
in_int_ena_ch0: IN_INT_ENA_CH0x10 - Interrupt enable bits of Rx channel 0
in_int_clr_ch0: IN_INT_CLR_CH0x14 - Interrupt clear bits of Rx channel 0
infifo_status_ch0: INFIFO_STATUS_CH0x18 - Receive FIFO status of Rx channel 0
in_pop_ch0: IN_POP_CH0x1c - Pop control register of Rx channel 0
in_link_ch0: IN_LINK_CH0x20 - Link descriptor configure and control register of Rx channel 0
in_state_ch0: IN_STATE_CH0x24 - Receive status of Rx channel 0
in_suc_eof_des_addr_ch0: IN_SUC_EOF_DES_ADDR_CH0x28 - Inlink descriptor address when EOF occurs of Rx channel 0
in_err_eof_des_addr_ch0: IN_ERR_EOF_DES_ADDR_CH0x2c - Inlink descriptor address when errors occur of Rx channel 0
in_dscr_ch0: IN_DSCR_CH0x30 - Current inlink descriptor address of Rx channel 0
in_dscr_bf0_ch0: IN_DSCR_BF0_CH0x34 - The last inlink descriptor address of Rx channel 0
in_dscr_bf1_ch0: IN_DSCR_BF1_CH0x38 - The second-to-last inlink descriptor address of Rx channel 0
in_wight_ch0: IN_WIGHT_CH0x3c - Weight register of Rx channel 0
in_pri_ch0: IN_PRI_CH0x44 - Priority register of Rx channel 0
in_peri_sel_ch0: IN_PERI_SEL_CH0x48 - Peripheral selection of Rx channel 0
out_conf0_ch0: OUT_CONF0_CH0x60 - Configure 0 register of Tx channel 0
out_conf1_ch0: OUT_CONF1_CH0x64 - Configure 1 register of Tx channel 0
out_int_raw_ch0: OUT_INT_RAW_CH0x68 - Raw status interrupt of Tx channel 0
out_int_st_ch0: OUT_INT_ST_CH0x6c - Masked interrupt of Tx channel 0
out_int_ena_ch0: OUT_INT_ENA_CH0x70 - Interrupt enable bits of Tx channel 0
out_int_clr_ch0: OUT_INT_CLR_CH0x74 - Interrupt clear bits of Tx channel 0
outfifo_status_ch0: OUTFIFO_STATUS_CH0x78 - Transmit FIFO status of Tx channel 0
out_push_ch0: OUT_PUSH_CH0x7c - Push control register of Rx channel 0
out_link_ch0: OUT_LINK_CH0x80 - Link descriptor configure and control register of Tx channel 0
out_state_ch0: OUT_STATE_CH0x84 - Transmit status of Tx channel 0
out_eof_des_addr_ch0: OUT_EOF_DES_ADDR_CH0x88 - Outlink descriptor address when EOF occurs of Tx channel 0
out_eof_bfr_des_addr_ch0: OUT_EOF_BFR_DES_ADDR_CH0x8c - The last outlink descriptor address when EOF occurs of Tx channel 0
out_dscr_ch0: OUT_DSCR_CH0x90 - Current inlink descriptor address of Tx channel 0
out_dscr_bf0_ch0: OUT_DSCR_BF0_CH0x94 - The last inlink descriptor address of Tx channel 0
out_dscr_bf1_ch0: OUT_DSCR_BF1_CH0x98 - The second-to-last inlink descriptor address of Tx channel 0
out_wight_ch0: OUT_WIGHT_CH0x9c - Weight register of Rx channel 0
out_pri_ch0: OUT_PRI_CH0xa4 - Priority register of Tx channel 0.
out_peri_sel_ch0: OUT_PERI_SEL_CH0xa8 - Peripheral selection of Tx channel 0
in_conf0_ch1: IN_CONF0_CH0xc0 - Configure 0 register of Rx channel 0
in_conf1_ch1: IN_CONF1_CH0xc4 - Configure 1 register of Rx channel 0
in_int_raw_ch1: IN_INT_RAW_CH0xc8 - Raw status interrupt of Rx channel 0
in_int_st_ch1: IN_INT_ST_CH0xcc - Masked interrupt of Rx channel 0
in_int_ena_ch1: IN_INT_ENA_CH0xd0 - Interrupt enable bits of Rx channel 0
in_int_clr_ch1: IN_INT_CLR_CH0xd4 - Interrupt clear bits of Rx channel 0
infifo_status_ch1: INFIFO_STATUS_CH0xd8 - Receive FIFO status of Rx channel 0
in_pop_ch1: IN_POP_CH0xdc - Pop control register of Rx channel 0
in_link_ch1: IN_LINK_CH0xe0 - Link descriptor configure and control register of Rx channel 0
in_state_ch1: IN_STATE_CH0xe4 - Receive status of Rx channel 0
in_suc_eof_des_addr_ch1: IN_SUC_EOF_DES_ADDR_CH0xe8 - Inlink descriptor address when EOF occurs of Rx channel 0
in_err_eof_des_addr_ch1: IN_ERR_EOF_DES_ADDR_CH0xec - Inlink descriptor address when errors occur of Rx channel 0
in_dscr_ch1: IN_DSCR_CH0xf0 - Current inlink descriptor address of Rx channel 0
in_dscr_bf0_ch1: IN_DSCR_BF0_CH0xf4 - The last inlink descriptor address of Rx channel 0
in_dscr_bf1_ch1: IN_DSCR_BF1_CH0xf8 - The second-to-last inlink descriptor address of Rx channel 0
in_wight_ch1: IN_WIGHT_CH0xfc - Weight register of Rx channel 0
in_pri_ch1: IN_PRI_CH0x104 - Priority register of Rx channel 0
in_peri_sel_ch1: IN_PERI_SEL_CH0x108 - Peripheral selection of Rx channel 0
out_conf0_ch1: OUT_CONF0_CH0x120 - Configure 0 register of Tx channel 0
out_conf1_ch1: OUT_CONF1_CH0x124 - Configure 1 register of Tx channel 0
out_int_raw_ch1: OUT_INT_RAW_CH0x128 - Raw status interrupt of Tx channel 0
out_int_st_ch1: OUT_INT_ST_CH0x12c - Masked interrupt of Tx channel 0
out_int_ena_ch1: OUT_INT_ENA_CH0x130 - Interrupt enable bits of Tx channel 0
out_int_clr_ch1: OUT_INT_CLR_CH0x134 - Interrupt clear bits of Tx channel 0
outfifo_status_ch1: OUTFIFO_STATUS_CH0x138 - Transmit FIFO status of Tx channel 0
out_push_ch1: OUT_PUSH_CH0x13c - Push control register of Rx channel 0
out_link_ch1: OUT_LINK_CH0x140 - Link descriptor configure and control register of Tx channel 0
out_state_ch1: OUT_STATE_CH0x144 - Transmit status of Tx channel 0
out_eof_des_addr_ch1: OUT_EOF_DES_ADDR_CH0x148 - Outlink descriptor address when EOF occurs of Tx channel 0
out_eof_bfr_des_addr_ch1: OUT_EOF_BFR_DES_ADDR_CH0x14c - The last outlink descriptor address when EOF occurs of Tx channel 0
out_dscr_ch1: OUT_DSCR_CH0x150 - Current inlink descriptor address of Tx channel 0
out_dscr_bf0_ch1: OUT_DSCR_BF0_CH0x154 - The last inlink descriptor address of Tx channel 0
out_dscr_bf1_ch1: OUT_DSCR_BF1_CH0x158 - The second-to-last inlink descriptor address of Tx channel 0
out_wight_ch1: OUT_WIGHT_CH0x15c - Weight register of Rx channel 0
out_pri_ch1: OUT_PRI_CH0x164 - Priority register of Tx channel 0.
out_peri_sel_ch1: OUT_PERI_SEL_CH0x168 - Peripheral selection of Tx channel 0
in_conf0_ch2: IN_CONF0_CH0x180 - Configure 0 register of Rx channel 0
in_conf1_ch2: IN_CONF1_CH0x184 - Configure 1 register of Rx channel 0
in_int_raw_ch2: IN_INT_RAW_CH0x188 - Raw status interrupt of Rx channel 0
in_int_st_ch2: IN_INT_ST_CH0x18c - Masked interrupt of Rx channel 0
in_int_ena_ch2: IN_INT_ENA_CH0x190 - Interrupt enable bits of Rx channel 0
in_int_clr_ch2: IN_INT_CLR_CH0x194 - Interrupt clear bits of Rx channel 0
infifo_status_ch2: INFIFO_STATUS_CH0x198 - Receive FIFO status of Rx channel 0
in_pop_ch2: IN_POP_CH0x19c - Pop control register of Rx channel 0
in_link_ch2: IN_LINK_CH0x1a0 - Link descriptor configure and control register of Rx channel 0
in_state_ch2: IN_STATE_CH0x1a4 - Receive status of Rx channel 0
in_suc_eof_des_addr_ch2: IN_SUC_EOF_DES_ADDR_CH0x1a8 - Inlink descriptor address when EOF occurs of Rx channel 0
in_err_eof_des_addr_ch2: IN_ERR_EOF_DES_ADDR_CH0x1ac - Inlink descriptor address when errors occur of Rx channel 0
in_dscr_ch2: IN_DSCR_CH0x1b0 - Current inlink descriptor address of Rx channel 0
in_dscr_bf0_ch2: IN_DSCR_BF0_CH0x1b4 - The last inlink descriptor address of Rx channel 0
in_dscr_bf1_ch2: IN_DSCR_BF1_CH0x1b8 - The second-to-last inlink descriptor address of Rx channel 0
in_wight_ch2: IN_WIGHT_CH0x1bc - Weight register of Rx channel 0
in_pri_ch2: IN_PRI_CH0x1c4 - Priority register of Rx channel 0
in_peri_sel_ch2: IN_PERI_SEL_CH0x1c8 - Peripheral selection of Rx channel 0
out_conf0_ch2: OUT_CONF0_CH0x1e0 - Configure 0 register of Tx channel 0
out_conf1_ch2: OUT_CONF1_CH0x1e4 - Configure 1 register of Tx channel 0
out_int_raw_ch2: OUT_INT_RAW_CH0x1e8 - Raw status interrupt of Tx channel 0
out_int_st_ch2: OUT_INT_ST_CH0x1ec - Masked interrupt of Tx channel 0
out_int_ena_ch2: OUT_INT_ENA_CH0x1f0 - Interrupt enable bits of Tx channel 0
out_int_clr_ch2: OUT_INT_CLR_CH0x1f4 - Interrupt clear bits of Tx channel 0
outfifo_status_ch2: OUTFIFO_STATUS_CH0x1f8 - Transmit FIFO status of Tx channel 0
out_push_ch2: OUT_PUSH_CH0x1fc - Push control register of Rx channel 0
out_link_ch2: OUT_LINK_CH0x200 - Link descriptor configure and control register of Tx channel 0
out_state_ch2: OUT_STATE_CH0x204 - Transmit status of Tx channel 0
out_eof_des_addr_ch2: OUT_EOF_DES_ADDR_CH0x208 - Outlink descriptor address when EOF occurs of Tx channel 0
out_eof_bfr_des_addr_ch2: OUT_EOF_BFR_DES_ADDR_CH0x20c - The last outlink descriptor address when EOF occurs of Tx channel 0
out_dscr_ch2: OUT_DSCR_CH0x210 - Current inlink descriptor address of Tx channel 0
out_dscr_bf0_ch2: OUT_DSCR_BF0_CH0x214 - The last inlink descriptor address of Tx channel 0
out_dscr_bf1_ch2: OUT_DSCR_BF1_CH0x218 - The second-to-last inlink descriptor address of Tx channel 0
out_wight_ch2: OUT_WIGHT_CH0x21c - Weight register of Rx channel 0
out_pri_ch2: OUT_PRI_CH0x224 - Priority register of Tx channel 0.
out_peri_sel_ch2: OUT_PERI_SEL_CH0x228 - Peripheral selection of Tx channel 0
in_conf0_ch3: IN_CONF0_CH0x240 - Configure 0 register of Rx channel 0
in_conf1_ch3: IN_CONF1_CH0x244 - Configure 1 register of Rx channel 0
in_int_raw_ch3: IN_INT_RAW_CH0x248 - Raw status interrupt of Rx channel 0
in_int_st_ch3: IN_INT_ST_CH0x24c - Masked interrupt of Rx channel 0
in_int_ena_ch3: IN_INT_ENA_CH0x250 - Interrupt enable bits of Rx channel 0
in_int_clr_ch3: IN_INT_CLR_CH0x254 - Interrupt clear bits of Rx channel 0
infifo_status_ch3: INFIFO_STATUS_CH0x258 - Receive FIFO status of Rx channel 0
in_pop_ch3: IN_POP_CH0x25c - Pop control register of Rx channel 0
in_link_ch3: IN_LINK_CH0x260 - Link descriptor configure and control register of Rx channel 0
in_state_ch3: IN_STATE_CH0x264 - Receive status of Rx channel 0
in_suc_eof_des_addr_ch3: IN_SUC_EOF_DES_ADDR_CH0x268 - Inlink descriptor address when EOF occurs of Rx channel 0
in_err_eof_des_addr_ch3: IN_ERR_EOF_DES_ADDR_CH0x26c - Inlink descriptor address when errors occur of Rx channel 0
in_dscr_ch3: IN_DSCR_CH0x270 - Current inlink descriptor address of Rx channel 0
in_dscr_bf0_ch3: IN_DSCR_BF0_CH0x274 - The last inlink descriptor address of Rx channel 0
in_dscr_bf1_ch3: IN_DSCR_BF1_CH0x278 - The second-to-last inlink descriptor address of Rx channel 0
in_wight_ch3: IN_WIGHT_CH0x27c - Weight register of Rx channel 0
in_pri_ch3: IN_PRI_CH0x284 - Priority register of Rx channel 0
in_peri_sel_ch3: IN_PERI_SEL_CH0x288 - Peripheral selection of Rx channel 0
out_conf0_ch3: OUT_CONF0_CH0x2a0 - Configure 0 register of Tx channel 0
out_conf1_ch3: OUT_CONF1_CH0x2a4 - Configure 1 register of Tx channel 0
out_int_raw_ch3: OUT_INT_RAW_CH0x2a8 - Raw status interrupt of Tx channel 0
out_int_st_ch3: OUT_INT_ST_CH0x2ac - Masked interrupt of Tx channel 0
out_int_ena_ch3: OUT_INT_ENA_CH0x2b0 - Interrupt enable bits of Tx channel 0
out_int_clr_ch3: OUT_INT_CLR_CH0x2b4 - Interrupt clear bits of Tx channel 0
outfifo_status_ch3: OUTFIFO_STATUS_CH0x2b8 - Transmit FIFO status of Tx channel 0
out_push_ch3: OUT_PUSH_CH0x2bc - Push control register of Rx channel 0
out_link_ch3: OUT_LINK_CH0x2c0 - Link descriptor configure and control register of Tx channel 0
out_state_ch3: OUT_STATE_CH0x2c4 - Transmit status of Tx channel 0
out_eof_des_addr_ch3: OUT_EOF_DES_ADDR_CH0x2c8 - Outlink descriptor address when EOF occurs of Tx channel 0
out_eof_bfr_des_addr_ch3: OUT_EOF_BFR_DES_ADDR_CH0x2cc - The last outlink descriptor address when EOF occurs of Tx channel 0
out_dscr_ch3: OUT_DSCR_CH0x2d0 - Current inlink descriptor address of Tx channel 0
out_dscr_bf0_ch3: OUT_DSCR_BF0_CH0x2d4 - The last inlink descriptor address of Tx channel 0
out_dscr_bf1_ch3: OUT_DSCR_BF1_CH0x2d8 - The second-to-last inlink descriptor address of Tx channel 0
out_wight_ch3: OUT_WIGHT_CH0x2dc - Weight register of Rx channel 0
out_pri_ch3: OUT_PRI_CH0x2e4 - Priority register of Tx channel 0.
out_peri_sel_ch3: OUT_PERI_SEL_CH0x2e8 - Peripheral selection of Tx channel 0
in_conf0_ch4: IN_CONF0_CH0x300 - Configure 0 register of Rx channel 0
in_conf1_ch4: IN_CONF1_CH0x304 - Configure 1 register of Rx channel 0
in_int_raw_ch4: IN_INT_RAW_CH0x308 - Raw status interrupt of Rx channel 0
in_int_st_ch4: IN_INT_ST_CH0x30c - Masked interrupt of Rx channel 0
in_int_ena_ch4: IN_INT_ENA_CH0x310 - Interrupt enable bits of Rx channel 0
in_int_clr_ch4: IN_INT_CLR_CH0x314 - Interrupt clear bits of Rx channel 0
infifo_status_ch4: INFIFO_STATUS_CH0x318 - Receive FIFO status of Rx channel 0
in_pop_ch4: IN_POP_CH0x31c - Pop control register of Rx channel 0
in_link_ch4: IN_LINK_CH0x320 - Link descriptor configure and control register of Rx channel 0
in_state_ch4: IN_STATE_CH0x324 - Receive status of Rx channel 0
in_suc_eof_des_addr_ch4: IN_SUC_EOF_DES_ADDR_CH0x328 - Inlink descriptor address when EOF occurs of Rx channel 0
in_err_eof_des_addr_ch4: IN_ERR_EOF_DES_ADDR_CH0x32c - Inlink descriptor address when errors occur of Rx channel 0
in_dscr_ch4: IN_DSCR_CH0x330 - Current inlink descriptor address of Rx channel 0
in_dscr_bf0_ch4: IN_DSCR_BF0_CH0x334 - The last inlink descriptor address of Rx channel 0
in_dscr_bf1_ch4: IN_DSCR_BF1_CH0x338 - The second-to-last inlink descriptor address of Rx channel 0
in_wight_ch4: IN_WIGHT_CH0x33c - Weight register of Rx channel 0
in_pri_ch4: IN_PRI_CH0x344 - Priority register of Rx channel 0
in_peri_sel_ch4: IN_PERI_SEL_CH0x348 - Peripheral selection of Rx channel 0
out_conf0_ch4: OUT_CONF0_CH0x360 - Configure 0 register of Tx channel 0
out_conf1_ch4: OUT_CONF1_CH0x364 - Configure 1 register of Tx channel 0
out_int_raw_ch4: OUT_INT_RAW_CH0x368 - Raw status interrupt of Tx channel 0
out_int_st_ch4: OUT_INT_ST_CH0x36c - Masked interrupt of Tx channel 0
out_int_ena_ch4: OUT_INT_ENA_CH0x370 - Interrupt enable bits of Tx channel 0
out_int_clr_ch4: OUT_INT_CLR_CH0x374 - Interrupt clear bits of Tx channel 0
outfifo_status_ch4: OUTFIFO_STATUS_CH0x378 - Transmit FIFO status of Tx channel 0
out_push_ch4: OUT_PUSH_CH0x37c - Push control register of Rx channel 0
out_link_ch4: OUT_LINK_CH0x380 - Link descriptor configure and control register of Tx channel 0
out_state_ch4: OUT_STATE_CH0x384 - Transmit status of Tx channel 0
out_eof_des_addr_ch4: OUT_EOF_DES_ADDR_CH0x388 - Outlink descriptor address when EOF occurs of Tx channel 0
out_eof_bfr_des_addr_ch4: OUT_EOF_BFR_DES_ADDR_CH0x38c - The last outlink descriptor address when EOF occurs of Tx channel 0
out_dscr_ch4: OUT_DSCR_CH0x390 - Current inlink descriptor address of Tx channel 0
out_dscr_bf0_ch4: OUT_DSCR_BF0_CH0x394 - The last inlink descriptor address of Tx channel 0
out_dscr_bf1_ch4: OUT_DSCR_BF1_CH0x398 - The second-to-last inlink descriptor address of Tx channel 0
out_wight_ch4: OUT_WIGHT_CH0x39c - Weight register of Rx channel 0
out_pri_ch4: OUT_PRI_CH0x3a4 - Priority register of Tx channel 0.
out_peri_sel_ch4: OUT_PERI_SEL_CH0x3a8 - Peripheral selection of Tx channel 0
ahb_test: AHB_TEST0x3c0 - reserved
pd_conf: PD_CONF0x3c4 - reserved
misc_conf: MISC_CONF0x3c8 - MISC register
in_sram_size_ch0: IN_SRAM_SIZE_CH0x3cc - Receive L2 FIFO depth of Rx channel 0
out_sram_size_ch0: OUT_SRAM_SIZE_CH0x3d0 - Transmit L2 FIFO depth of Tx channel 0
in_sram_size_ch1: IN_SRAM_SIZE_CH0x3d4 - Receive L2 FIFO depth of Rx channel 0
out_sram_size_ch1: OUT_SRAM_SIZE_CH0x3d8 - Transmit L2 FIFO depth of Tx channel 0
in_sram_size_ch2: IN_SRAM_SIZE_CH0x3dc - Receive L2 FIFO depth of Rx channel 0
out_sram_size_ch2: OUT_SRAM_SIZE_CH0x3e0 - Transmit L2 FIFO depth of Tx channel 0
in_sram_size_ch3: IN_SRAM_SIZE_CH0x3e4 - Receive L2 FIFO depth of Rx channel 0
out_sram_size_ch3: OUT_SRAM_SIZE_CH0x3e8 - Transmit L2 FIFO depth of Tx channel 0
in_sram_size_ch4: IN_SRAM_SIZE_CH0x3ec - Receive L2 FIFO depth of Rx channel 0
out_sram_size_ch4: OUT_SRAM_SIZE_CH0x3f0 - Transmit L2 FIFO depth of Tx channel 0
extmem_reject_addr: EXTMEM_REJECT_ADDR0x3f4 - Reject address accessing external RAM
extmem_reject_st: EXTMEM_REJECT_ST0x3f8 - Reject status accessing external RAM
extmem_reject_int_raw: EXTMEM_REJECT_INT_RAW0x3fc - Raw interrupt status of external RAM permission
extmem_reject_int_st: EXTMEM_REJECT_INT_ST0x400 - Masked interrupt status of external RAM permission
extmem_reject_int_ena: EXTMEM_REJECT_INT_ENA0x404 - Interrupt enable bits of external RAM permission
extmem_reject_int_clr: EXTMEM_REJECT_INT_CLR0x408 - Interrupt clear bits of external RAM permission
date: DATE0x40c - Version control register