Struct esp32s3::spi0::sram_cmd::W

pub struct W(_);

Register SRAM_CMD writer

Implementations

impl W

pub fn sclk_mode(&mut self) -> SCLK_MODE_W<'_, 0>

Bits 0:1 - SPI_CLK mode bits when SPI0 accesses to Ext_RAM. 0: SPI_CLK is off when CS inactive 1: SPI_CLK is delayed one cycle after CS inactive 2: SPI_CLK is delayed two cycles after CS inactive 3: SPI_CLK is always on.

pub fn swb_mode(&mut self) -> SWB_MODE_W<'_, 2>

Bits 2:9 - Mode bits when SPI0 accesses to Ext_RAM.

pub fn sdin_dual(&mut self) -> SDIN_DUAL_W<'_, 10>

Bit 10 - When SPI0 accesses to Ext_RAM, set this bit to enable 2-bm in DIN phase.

pub fn sdout_dual(&mut self) -> SDOUT_DUAL_W<'_, 11>

Bit 11 - When SPI0 accesses to Ext_RAM, set this bit to enable 2-bm in DOUT phase.

pub fn saddr_dual(&mut self) -> SADDR_DUAL_W<'_, 12>

Bit 12 - When SPI0 accesses to Ext_RAM, set this bit to enable 2-bm in ADDR phase.

pub fn scmd_dual(&mut self) -> SCMD_DUAL_W<'_, 13>

Bit 13 - When SPI0 accesses to Ext_RAM, set this bit to enable 2-bm in CMD phase.

pub fn sdin_quad(&mut self) -> SDIN_QUAD_W<'_, 14>

Bit 14 - When SPI0 accesses to Ext_RAM, set this bit to enable 4-bm in DIN phase.

pub fn sdout_quad(&mut self) -> SDOUT_QUAD_W<'_, 15>

Bit 15 - When SPI0 accesses to Ext_RAM, set this bit to enable 4-bm in DOUT phase.

pub fn saddr_quad(&mut self) -> SADDR_QUAD_W<'_, 16>

Bit 16 - When SPI0 accesses to Ext_RAM, set this bit to enable 4-bm in ADDR phase.

pub fn scmd_quad(&mut self) -> SCMD_QUAD_W<'_, 17>

Bit 17 - When SPI0 accesses to Ext_RAM, set this bit to enable 4-bm in CMD phase.

pub fn sdin_oct(&mut self) -> SDIN_OCT_W<'_, 18>

Bit 18 - When SPI0 accesses to Ext_RAM, set this bit to enable 8-bm in DIN phase.

pub fn sdout_oct(&mut self) -> SDOUT_OCT_W<'_, 19>

Bit 19 - When SPI0 accesses to Ext_RAM, set this bit to enable 8-bm in DOUT phase.

pub fn saddr_oct(&mut self) -> SADDR_OCT_W<'_, 20>

Bit 20 - When SPI0 accesses to Ext_RAM, set this bit to enable 8-bm in ADDR phase.

pub fn scmd_oct(&mut self) -> SCMD_OCT_W<'_, 21>

Bit 21 - When SPI0 accesses to Ext_RAM, set this bit to enable 8-bm in CMD phase.

pub fn sdummy_out(&mut self) -> SDUMMY_OUT_W<'_, 22>

Bit 22 - When SPI0 accesses to Ext_RAM, in the DUMMY phase the signal level of SPI bus is output by the SPI0 controller.

pub unsafe fn bits(&mut self, bits: u32) -> &mut Self

Writes raw bits to the register.

Methods from Deref<Target = W<SRAM_CMD_SPEC>>

pub unsafe fn bits(&mut self, bits: REG::Ux) -> &mut Self

Writes raw bits to the register.

Safety

Read datasheet or reference manual to find what values are allowed to pass.

Trait Implementations

impl Deref for W

type Target = W<SRAM_CMD_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &Self::Target

Dereferences the value.

impl DerefMut for W

fn deref_mut(&mut self) -> &mut Self::Target

Mutably dereferences the value.

impl From<W<SRAM_CMD_SPEC>> for W

fn from(writer: W<SRAM_CMD_SPEC>) -> Self

Converts to this type from the input type.