Module esp32s3::lcd_cam::lcd_clock

LCD clock register

Structs

• LCD_CLOCK_SPEC
  LCD clock register
• R
  Register LCD_CLOCK reader
• W
  Register LCD_CLOCK writer

Type Definitions

• CLK_EN_R
  Field CLK_EN reader - Set this bit to enable clk gate
• CLK_EN_W
  Field CLK_EN writer - Set this bit to enable clk gate
• LCD_CK_IDLE_EDGE_R
  Field LCD_CK_IDLE_EDGE reader - 1: LCD_PCLK line is high when idle 0: LCD_PCLK line is low when idle.
• LCD_CK_IDLE_EDGE_W
  Field LCD_CK_IDLE_EDGE writer - 1: LCD_PCLK line is high when idle 0: LCD_PCLK line is low when idle.
• LCD_CK_OUT_EDGE_R
  Field LCD_CK_OUT_EDGE reader - 1: LCD_PCLK high in first half clock cycle. 0: LCD_PCLK low in first half clock cycle.
• LCD_CK_OUT_EDGE_W
  Field LCD_CK_OUT_EDGE writer - 1: LCD_PCLK high in first half clock cycle. 0: LCD_PCLK low in first half clock cycle.
• LCD_CLKCNT_N_R
  Field LCD_CLKCNT_N reader - f_LCD_PCLK = f_LCD_CLK / (reg_clkcnt_N + 1) when reg_clk_equ_sysclk is 0.
• LCD_CLKCNT_N_W
  Field LCD_CLKCNT_N writer - f_LCD_PCLK = f_LCD_CLK / (reg_clkcnt_N + 1) when reg_clk_equ_sysclk is 0.
• LCD_CLKM_DIV_A_R
  Field LCD_CLKM_DIV_A reader - Fractional clock divider denominator value
• LCD_CLKM_DIV_A_W
  Field LCD_CLKM_DIV_A writer - Fractional clock divider denominator value
• LCD_CLKM_DIV_B_R
  Field LCD_CLKM_DIV_B reader - Fractional clock divider numerator value
• LCD_CLKM_DIV_B_W
  Field LCD_CLKM_DIV_B writer - Fractional clock divider numerator value
• LCD_CLKM_DIV_NUM_R
  Field LCD_CLKM_DIV_NUM reader - Integral LCD clock divider value
• LCD_CLKM_DIV_NUM_W
  Field LCD_CLKM_DIV_NUM writer - Integral LCD clock divider value
• LCD_CLK_EQU_SYSCLK_R
  Field LCD_CLK_EQU_SYSCLK reader - 1: f_LCD_PCLK = f_LCD_CLK. 0: f_LCD_PCLK = f_LCD_CLK / (reg_clkcnt_N + 1).
• LCD_CLK_EQU_SYSCLK_W
  Field LCD_CLK_EQU_SYSCLK writer - 1: f_LCD_PCLK = f_LCD_CLK. 0: f_LCD_PCLK = f_LCD_CLK / (reg_clkcnt_N + 1).
• LCD_CLK_SEL_R
  Field LCD_CLK_SEL reader - Select LCD module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: no clock.
• LCD_CLK_SEL_W
  Field LCD_CLK_SEL writer - Select LCD module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: no clock.