pub struct W(_);
Expand description
Register TX_TIMING
writer
Implementations§
source§impl W
impl W
sourcepub fn tx_sd_out_dm(&mut self) -> TX_SD_OUT_DM_W<'_, 0>
pub fn tx_sd_out_dm(&mut self) -> TX_SD_OUT_DM_W<'_, 0>
Bits 0:1 - The delay mode of I2S TX SD output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.
sourcepub fn tx_sd1_out_dm(&mut self) -> TX_SD1_OUT_DM_W<'_, 4>
pub fn tx_sd1_out_dm(&mut self) -> TX_SD1_OUT_DM_W<'_, 4>
Bits 4:5 - The delay mode of I2S TX SD1 output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.
sourcepub fn tx_ws_out_dm(&mut self) -> TX_WS_OUT_DM_W<'_, 16>
pub fn tx_ws_out_dm(&mut self) -> TX_WS_OUT_DM_W<'_, 16>
Bits 16:17 - The delay mode of I2S TX WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.
sourcepub fn tx_bck_out_dm(&mut self) -> TX_BCK_OUT_DM_W<'_, 20>
pub fn tx_bck_out_dm(&mut self) -> TX_BCK_OUT_DM_W<'_, 20>
Bits 20:21 - The delay mode of I2S TX BCK output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.
sourcepub fn tx_ws_in_dm(&mut self) -> TX_WS_IN_DM_W<'_, 24>
pub fn tx_ws_in_dm(&mut self) -> TX_WS_IN_DM_W<'_, 24>
Bits 24:25 - The delay mode of I2S TX WS input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.
sourcepub fn tx_bck_in_dm(&mut self) -> TX_BCK_IN_DM_W<'_, 28>
pub fn tx_bck_in_dm(&mut self) -> TX_BCK_IN_DM_W<'_, 28>
Bits 28:29 - The delay mode of I2S TX BCK input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.