Struct esp32s3::i2s0::tx_conf1::W

pub struct W(_);

Register TX_CONF1 writer

Implementations

impl W

pub fn tx_tdm_ws_width(&mut self) -> TX_TDM_WS_WIDTH_W<'_, 0>

Bits 0:6 - The width of tx_ws_out in TDM mode is (I2S_TX_TDM_WS_WIDTH[6:0] +1) * T_bck

pub fn tx_bck_div_num(&mut self) -> TX_BCK_DIV_NUM_W<'_, 7>

Bits 7:12 - Bit clock configuration bits in transmitter mode.

pub fn tx_bits_mod(&mut self) -> TX_BITS_MOD_W<'_, 13>

Bits 13:17 - Set the bits to configure the valid data bit length of I2S transmitter channel. 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode.

pub fn tx_half_sample_bits(&mut self) -> TX_HALF_SAMPLE_BITS_W<'_, 18>

Bits 18:23 - I2S Tx half sample bits -1.

pub fn tx_tdm_chan_bits(&mut self) -> TX_TDM_CHAN_BITS_W<'_, 24>

Bits 24:28 - The Tx bit number for each channel minus 1in TDM mode.

pub fn tx_msb_shift(&mut self) -> TX_MSB_SHIFT_W<'_, 29>

Bit 29 - Set this bit to enable transmitter in Phillips standard mode

pub fn tx_bck_no_dly(&mut self) -> TX_BCK_NO_DLY_W<'_, 30>

Bit 30 - 1: BCK is not delayed to generate pos/neg edge in master mode. 0: BCK is delayed to generate pos/neg edge in master mode.

pub unsafe fn bits(&mut self, bits: u32) -> &mut Self

Writes raw bits to the register.

Methods from Deref<Target = W<TX_CONF1_SPEC>>

pub unsafe fn bits(&mut self, bits: REG::Ux) -> &mut Self

Writes raw bits to the register.

Safety

Read datasheet or reference manual to find what values are allowed to pass.

Trait Implementations

impl Deref for W

type Target = W<TX_CONF1_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &Self::Target

Dereferences the value.

impl DerefMut for W

fn deref_mut(&mut self) -> &mut Self::Target

Mutably dereferences the value.

impl From<W<TX_CONF1_SPEC>> for W

fn from(writer: W<TX_CONF1_SPEC>) -> Self

Converts to this type from the input type.