Struct esp32s3::extmem::cache_sync_int_ctrl::R

pub struct R(_);

Register CACHE_SYNC_INT_CTRL reader

Implementations

impl R

pub fn icache_sync_int_st(&self) -> ICACHE_SYNC_INT_ST_R

Bit 0 - The bit is used to indicate the interrupt by icache sync done.

pub fn icache_sync_int_ena(&self) -> ICACHE_SYNC_INT_ENA_R

Bit 1 - The bit is used to enable the interrupt by icache sync done.

pub fn dcache_sync_int_st(&self) -> DCACHE_SYNC_INT_ST_R

Bit 3 - The bit is used to indicate the interrupt by dcache sync done.

pub fn dcache_sync_int_ena(&self) -> DCACHE_SYNC_INT_ENA_R

Bit 4 - The bit is used to enable the interrupt by dcache sync done.

Methods from Deref<Target = R<CACHE_SYNC_INT_CTRL_SPEC>>

pub fn bits(&self) -> REG::Ux

Reads raw bits from register.

Trait Implementations

impl Deref for R

type Target = R<CACHE_SYNC_INT_CTRL_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &Self::Target

Dereferences the value.

impl From<R<CACHE_SYNC_INT_CTRL_SPEC>> for R

fn from(reader: R<CACHE_SYNC_INT_CTRL_SPEC>) -> Self

Converts to this type from the input type.