Struct esp32s3::spi2::misc::R

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pub struct R(_);

Expand description

Register MISC reader

Implementations§

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impl R

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pub fn cs0_dis(&self) -> CS0_DIS_R

Bit 0 - SPI CS0 pin enable, 1: disable CS0, 0: spi_cs0 signal is from/to CS0 pin. Can be configured in CONF state.

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pub fn cs1_dis(&self) -> CS1_DIS_R

Bit 1 - SPI CS1 pin enable, 1: disable CS1, 0: spi_cs1 signal is from/to CS1 pin. Can be configured in CONF state.

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pub fn cs2_dis(&self) -> CS2_DIS_R

Bit 2 - SPI CS2 pin enable, 1: disable CS2, 0: spi_cs2 signal is from/to CS2 pin. Can be configured in CONF state.

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pub fn cs3_dis(&self) -> CS3_DIS_R

Bit 3 - SPI CS3 pin enable, 1: disable CS3, 0: spi_cs3 signal is from/to CS3 pin. Can be configured in CONF state.

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pub fn cs4_dis(&self) -> CS4_DIS_R

Bit 4 - SPI CS4 pin enable, 1: disable CS4, 0: spi_cs4 signal is from/to CS4 pin. Can be configured in CONF state.

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pub fn cs5_dis(&self) -> CS5_DIS_R

Bit 5 - SPI CS5 pin enable, 1: disable CS5, 0: spi_cs5 signal is from/to CS5 pin. Can be configured in CONF state.

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pub fn ck_dis(&self) -> CK_DIS_R

Bit 6 - 1: spi clk out disable, 0: spi clk out enable. Can be configured in CONF state.

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pub fn master_cs_pol(&self) -> MASTER_CS_POL_R

Bits 7:12 - In the master mode the bits are the polarity of spi cs line, the value is equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state.

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pub fn clk_data_dtr_en(&self) -> CLK_DATA_DTR_EN_R

Bit 16 - 1: SPI master DTR mode is applied to SPI clk, data and spi_dqs. 0: SPI master DTR mode is only applied to spi_dqs. This bit should be used with bit 17/18/19.

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pub fn data_dtr_en(&self) -> DATA_DTR_EN_R

Bit 17 - 1: SPI clk and data of SPI_DOUT and SPI_DIN state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_DOUT and SPI_DIN state are in STR mode. Can be configured in CONF state.

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pub fn addr_dtr_en(&self) -> ADDR_DTR_EN_R

Bit 18 - 1: SPI clk and data of SPI_SEND_ADDR state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_ADDR state are in STR mode. Can be configured in CONF state.

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pub fn cmd_dtr_en(&self) -> CMD_DTR_EN_R

Bit 19 - 1: SPI clk and data of SPI_SEND_CMD state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_CMD state are in STR mode. Can be configured in CONF state.

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pub fn slave_cs_pol(&self) -> SLAVE_CS_POL_R

Bit 23 - spi slave input cs polarity select. 1: inv 0: not change. Can be configured in CONF state.

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pub fn dqs_idle_edge(&self) -> DQS_IDLE_EDGE_R

Bit 24 - The default value of spi_dqs. Can be configured in CONF state.

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pub fn ck_idle_edge(&self) -> CK_IDLE_EDGE_R

Bit 29 - 1: spi clk line is high when idle 0: spi clk line is low when idle. Can be configured in CONF state.

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pub fn cs_keep_active(&self) -> CS_KEEP_ACTIVE_R

Bit 30 - spi cs line keep low when the bit is set. Can be configured in CONF state.

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pub fn quad_din_pin_swap(&self) -> QUAD_DIN_PIN_SWAP_R

Bit 31 - 1: SPI quad input swap enable, swap FSPID with FSPIQ, swap FSPIWP with FSPIHD. 0: spi quad input swap disable. Can be configured in CONF state.