Struct esp32s3::systimer::RegisterBlock

source · 
#[repr(C)]
pub struct RegisterBlock {
Show 36 fields
    pub conf: CONF,
    pub unit0_op: UNIT0_OP,
    pub unit1_op: UNIT1_OP,
    pub unit0_load_hi: UNIT0_LOAD_HI,
    pub unit0_load_lo: UNIT0_LOAD_LO,
    pub unit1_load_hi: UNIT1_LOAD_HI,
    pub unit1_load_lo: UNIT1_LOAD_LO,
    pub target0_hi: TARGET0_HI,
    pub target0_lo: TARGET0_LO,
    pub target1_hi: TARGET1_HI,
    pub target1_lo: TARGET1_LO,
    pub target2_hi: TARGET2_HI,
    pub target2_lo: TARGET2_LO,
    pub target0_conf: TARGET0_CONF,
    pub target1_conf: TARGET1_CONF,
    pub target2_conf: TARGET2_CONF,
    pub unit0_value_hi: UNIT0_VALUE_HI,
    pub unit0_value_lo: UNIT0_VALUE_LO,
    pub unit1_value_hi: UNIT1_VALUE_HI,
    pub unit1_value_lo: UNIT1_VALUE_LO,
    pub comp0_load: COMP0_LOAD,
    pub comp1_load: COMP1_LOAD,
    pub comp2_load: COMP2_LOAD,
    pub unit0_load: UNIT0_LOAD,
    pub unit1_load: UNIT1_LOAD,
    pub int_ena: INT_ENA,
    pub int_raw: INT_RAW,
    pub int_clr: INT_CLR,
    pub int_st: INT_ST,
    pub real_target0_lo: REAL_TARGET0_LO,
    pub real_target0_hi: REAL_TARGET0_HI,
    pub real_target1_lo: REAL_TARGET1_LO,
    pub real_target1_hi: REAL_TARGET1_HI,
    pub real_target2_lo: REAL_TARGET2_LO,
    pub real_target2_hi: REAL_TARGET2_HI,
    pub date: DATE,
    /* private fields */

}
Expand description

Register block

Fields§

§conf: CONF

0x00 - Configure system timer clock

§unit0_op: UNIT0_OP

0x04 - system timer unit0 value update register

§unit1_op: UNIT1_OP

0x08 - system timer unit1 value update register

§unit0_load_hi: UNIT0_LOAD_HI

0x0c - system timer unit0 value high load register

§unit0_load_lo: UNIT0_LOAD_LO

0x10 - system timer unit0 value low load register

§unit1_load_hi: UNIT1_LOAD_HI

0x14 - system timer unit1 value high load register

§unit1_load_lo: UNIT1_LOAD_LO

0x18 - system timer unit1 value low load register

§target0_hi: TARGET0_HI

0x1c - system timer comp0 value high register

§target0_lo: TARGET0_LO

0x20 - system timer comp0 value low register

§target1_hi: TARGET1_HI

0x24 - system timer comp1 value high register

§target1_lo: TARGET1_LO

0x28 - system timer comp1 value low register

§target2_hi: TARGET2_HI

0x2c - system timer comp2 value high register

§target2_lo: TARGET2_LO

0x30 - system timer comp2 value low register

§target0_conf: TARGET0_CONF

0x34 - system timer comp0 target mode register

§target1_conf: TARGET1_CONF

0x38 - system timer comp1 target mode register

§target2_conf: TARGET2_CONF

0x3c - system timer comp2 target mode register

§unit0_value_hi: UNIT0_VALUE_HI

0x40 - system timer unit0 value high register

§unit0_value_lo: UNIT0_VALUE_LO

0x44 - system timer unit0 value low register

§unit1_value_hi: UNIT1_VALUE_HI

0x48 - system timer unit1 value high register

§unit1_value_lo: UNIT1_VALUE_LO

0x4c - system timer unit1 value low register

§comp0_load: COMP0_LOAD

0x50 - system timer comp0 conf sync register

§comp1_load: COMP1_LOAD

0x54 - system timer comp1 conf sync register

§comp2_load: COMP2_LOAD

0x58 - system timer comp2 conf sync register

§unit0_load: UNIT0_LOAD

0x5c - system timer unit0 conf sync register

§unit1_load: UNIT1_LOAD

0x60 - system timer unit1 conf sync register

§int_ena: INT_ENA

0x64 - systimer interrupt enable register

§int_raw: INT_RAW

0x68 - systimer interrupt raw register

§int_clr: INT_CLR

0x6c - systimer interrupt clear register

§int_st: INT_ST

0x70 - systimer interrupt status register

§real_target0_lo: REAL_TARGET0_LO

0x74 - system timer comp0 actual target value low register

§real_target0_hi: REAL_TARGET0_HI

0x78 - system timer comp0 actual target value high register

§real_target1_lo: REAL_TARGET1_LO

0x7c - system timer comp1 actual target value low register

§real_target1_hi: REAL_TARGET1_HI

0x80 - system timer comp1 actual target value high register

§real_target2_lo: REAL_TARGET2_LO

0x84 - system timer comp2 actual target value low register

§real_target2_hi: REAL_TARGET2_HI

0x88 - system timer comp2 actual target value high register

§date: DATE

0xfc - system timer version control register

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