Module esp32s3::uhci0::conf1

Expand description

UHCI configuration register

Structs

UHCI configuration register

Register CONF1 reader

Register CONF1 writer

Field CHECK_SEQ_EN reader - This is the enable bit to check sequence number when UHCI receives a data packet.

Field CHECK_SEQ_EN writer - This is the enable bit to check sequence number when UHCI receives a data packet.

Field CHECK_SUM_EN reader - This is the enable bit to check header checksum when UHCI receives a data packet.

Field CHECK_SUM_EN writer - This is the enable bit to check header checksum when UHCI receives a data packet.

Field CRC_DISABLE reader - Set this bit to support CRC calculation. Data Integrity Check Present bit in UHCI packet frame should be 1.

Field CRC_DISABLE writer - Set this bit to support CRC calculation. Data Integrity Check Present bit in UHCI packet frame should be 1.

Field SAVE_HEAD reader - Set this bit to save the packet header when HCI receives a data packet.

Field SAVE_HEAD writer - Set this bit to save the packet header when HCI receives a data packet.

Field SW_START reader - If current UHCI_ENCODE_STATE is ST_SW_WAIT, the UHCI will start to send data packet out when this bit is set to 1.

Field SW_START writer - If current UHCI_ENCODE_STATE is ST_SW_WAIT, the UHCI will start to send data packet out when this bit is set to 1.

Field TX_ACK_NUM_RE reader - Set this bit to encode the data packet with an acknowledgment when a reliable packet is to be transmit.

Field TX_ACK_NUM_RE writer - Set this bit to encode the data packet with an acknowledgment when a reliable packet is to be transmit.

Field TX_CHECK_SUM_RE reader - Set this bit to encode the data packet with a checksum.

Field TX_CHECK_SUM_RE writer - Set this bit to encode the data packet with a checksum.

Field WAIT_SW_START reader - The uhci-encoder will jump to ST_SW_WAIT status if this register is set to 1.

Field WAIT_SW_START writer - The uhci-encoder will jump to ST_SW_WAIT status if this register is set to 1.