Struct esp32s3::extmem::dcache_lock_size::DCACHE_LOCK_SIZE_SPEC

pub struct DCACHE_LOCK_SIZE_SPEC;

******* Description ***********

This register you can read, write_with_zero, reset, write, modify. See API.

For information about available fields see dcache_lock_size module

Trait Implementations

impl Readable for DCACHE_LOCK_SIZE_SPEC

read() method returns dcache_lock_size::R reader structure

type Reader = R

Result from a call to read and argument to modify.

impl RegisterSpec for DCACHE_LOCK_SIZE_SPEC

type Ux = u32

Raw register type (u8, u16, u32, …).

impl Resettable for DCACHE_LOCK_SIZE_SPEC

reset() method sets DCACHE_LOCK_SIZE to value 0

const RESET_VALUE: Self::Ux = {transmute(0x00000000): <extmem::dcache_lock_size::DCACHE_LOCK_SIZE_SPEC as generic::RegisterSpec>::Ux}

Reset value of the register.

fn reset_value() -> Self::Ux

Reset value of the register.

impl Writable for DCACHE_LOCK_SIZE_SPEC

write(|w| ..) method takes dcache_lock_size::W writer structure

type Writer = W

Writer type argument to write, et al.

const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = {transmute(0x00000000): <extmem::dcache_lock_size::DCACHE_LOCK_SIZE_SPEC as generic::RegisterSpec>::Ux}

Specifies the register bits that are not changed if you pass 1 and are changed if you pass 0

const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = {transmute(0x00000000): <extmem::dcache_lock_size::DCACHE_LOCK_SIZE_SPEC as generic::RegisterSpec>::Ux}

Specifies the register bits that are not changed if you pass 0 and are changed if you pass 1