Struct esp32s3::spi0::cache_fctrl::R

pub struct R(_);

Register CACHE_FCTRL reader

Implementations

impl R

pub fn cache_req_en(&self) -> CACHE_REQ_EN_R

Bit 0 - Set this bit to enable Cache’s access and SPI0’s transfer.

pub fn cache_usr_cmd_4byte(&self) -> CACHE_USR_CMD_4BYTE_R

Bit 1 - Set this bit to enable SPI0 read flash with 32 bits address. The value of SPI_MEM_USR_ADDR_BITLEN should be 31.

pub fn cache_flash_usr_cmd(&self) -> CACHE_FLASH_USR_CMD_R

Bit 2 - 1: The command value of SPI0 reads flash is SPI_MEM_USR_COMMAND_VALUE. 0: Hardware read command value, controlled by SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QUAD, SPI_MEM_FREAD_DUAL and SPI_MEM_FASTRD_MODE bits.

pub fn fdin_dual(&self) -> FDIN_DUAL_R

Bit 3 - When SPI0 accesses to flash, set this bit to enable 2-bm in DIN phase.

pub fn fdout_dual(&self) -> FDOUT_DUAL_R

Bit 4 - When SPI0 accesses to flash, set this bit to enable 2-bm in DOUT phase.

pub fn faddr_dual(&self) -> FADDR_DUAL_R

Bit 5 - When SPI0 accesses to flash, set this bit to enable 2-bm in ADDR phase.

pub fn fdin_quad(&self) -> FDIN_QUAD_R

Bit 6 - When SPI0 accesses to flash, set this bit to enable 4-bm in DIN phase.

pub fn fdout_quad(&self) -> FDOUT_QUAD_R

Bit 7 - When SPI0 accesses to flash, set this bit to enable 4-bm in DOUT phase.

pub fn faddr_quad(&self) -> FADDR_QUAD_R

Bit 8 - When SPI0 accesses to flash, set this bit to enable 4-bm in ADDR phase.

Methods from Deref<Target = R<CACHE_FCTRL_SPEC>>

pub fn bits(&self) -> REG::Ux

Reads raw bits from register.

Trait Implementations

impl Deref for R

type Target = R<CACHE_FCTRL_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &Self::Target

Dereferences the value.

impl From<R<CACHE_FCTRL_SPEC>> for R

fn from(reader: R<CACHE_FCTRL_SPEC>) -> Self

Converts to this type from the input type.