Struct esp32s3::i2s1::RegisterBlock

source · 
#[repr(C)]
pub struct RegisterBlock {
Show 21 fields
    pub int_raw: INT_RAW,
    pub int_st: INT_ST,
    pub int_ena: INT_ENA,
    pub int_clr: INT_CLR,
    pub rx_conf: RX_CONF,
    pub tx_conf: TX_CONF,
    pub rx_conf1: RX_CONF1,
    pub tx_conf1: TX_CONF1,
    pub rx_clkm_conf: RX_CLKM_CONF,
    pub tx_clkm_conf: TX_CLKM_CONF,
    pub rx_clkm_div_conf: RX_CLKM_DIV_CONF,
    pub tx_clkm_div_conf: TX_CLKM_DIV_CONF,
    pub rx_tdm_ctrl: RX_TDM_CTRL,
    pub tx_tdm_ctrl: TX_TDM_CTRL,
    pub rx_timing: RX_TIMING,
    pub tx_timing: TX_TIMING,
    pub lc_hung_conf: LC_HUNG_CONF,
    pub rxeof_num: RXEOF_NUM,
    pub conf_sigle_data: CONF_SIGLE_DATA,
    pub state: STATE,
    pub date: DATE,
    /* private fields */

}
Expand description

Register block

Fields§

§int_raw: INT_RAW

0x0c - I2S interrupt raw register, valid in level.

§int_st: INT_ST

0x10 - I2S interrupt status register.

§int_ena: INT_ENA

0x14 - I2S interrupt enable register.

§int_clr: INT_CLR

0x18 - I2S interrupt clear register.

§rx_conf: RX_CONF

0x20 - I2S RX configure register

§tx_conf: TX_CONF

0x24 - I2S TX configure register

§rx_conf1: RX_CONF1

0x28 - I2S RX configure register 1

§tx_conf1: TX_CONF1

0x2c - I2S TX configure register 1

§rx_clkm_conf: RX_CLKM_CONF

0x30 - I2S RX clock configure register

§tx_clkm_conf: TX_CLKM_CONF

0x34 - I2S TX clock configure register

§rx_clkm_div_conf: RX_CLKM_DIV_CONF

0x38 - I2S RX module clock divider configure register

§tx_clkm_div_conf: TX_CLKM_DIV_CONF

0x3c - I2S TX module clock divider configure register

§rx_tdm_ctrl: RX_TDM_CTRL

0x50 - I2S TX TDM mode control register

§tx_tdm_ctrl: TX_TDM_CTRL

0x54 - I2S TX TDM mode control register

§rx_timing: RX_TIMING

0x58 - I2S RX timing control register

§tx_timing: TX_TIMING

0x5c - I2S TX timing control register

§lc_hung_conf: LC_HUNG_CONF

0x60 - I2S HUNG configure register.

§rxeof_num: RXEOF_NUM

0x64 - I2S RX data number control register.

§conf_sigle_data: CONF_SIGLE_DATA

0x68 - I2S signal data register

§state: STATE

0x6c - I2S TX status register

§date: DATE

0x80 - Version control register

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