Struct esp32s3::dma::out_int_clr_ch::OUT_INT_CLR_CH_SPEC

pub struct OUT_INT_CLR_CH_SPEC;

Interrupt clear bits of Tx channel 0

This register you can write_with_zero, reset, write. See API.

For information about available fields see out_int_clr_ch module

Trait Implementations

impl RegisterSpec for OUT_INT_CLR_CH_SPEC

type Ux = u32

Raw register type (u8, u16, u32, …).

impl Resettable for OUT_INT_CLR_CH_SPEC

reset() method sets OUT_INT_CLR_CH%s to value 0

const RESET_VALUE: Self::Ux = {transmute(0x00000000): <dma::out_int_clr_ch::OUT_INT_CLR_CH_SPEC as generic::RegisterSpec>::Ux}

Reset value of the register.

fn reset_value() -> Self::Ux

Reset value of the register.

impl Writable for OUT_INT_CLR_CH_SPEC

write(|w| ..) method takes out_int_clr_ch::W writer structure

type Writer = W

Writer type argument to write, et al.

const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = {transmute(0x00000000): <dma::out_int_clr_ch::OUT_INT_CLR_CH_SPEC as generic::RegisterSpec>::Ux}

Specifies the register bits that are not changed if you pass 1 and are changed if you pass 0

const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = {transmute(0x00000000): <dma::out_int_clr_ch::OUT_INT_CLR_CH_SPEC as generic::RegisterSpec>::Ux}

Specifies the register bits that are not changed if you pass 0 and are changed if you pass 1