Struct esp32s3::sensitive::core_1_pif_pms_constrain_5::R

pub struct R(_);

Register CORE_1_PIF_PMS_CONSTRAIN_5 reader

Implementations

impl R

pub fn core_1_pif_pms_constrain_world_1_uart(
    &self
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART_R

Bits 0:1 - Core1 access uart permission in world1.

pub fn core_1_pif_pms_constrain_world_1_g0spi_1(
    &self
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_R

Bits 2:3 - Core1 access g0spi_1 permission in world1.

pub fn core_1_pif_pms_constrain_world_1_g0spi_0(
    &self
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_R

Bits 4:5 - Core1 access g0spi_0 permission in world1.

pub fn core_1_pif_pms_constrain_world_1_gpio(
    &self
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_R

Bits 6:7 - Core1 access gpio permission in world1.

pub fn core_1_pif_pms_constrain_world_1_fe2(
    &self
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE2_R

Bits 8:9 - Core1 access fe2 permission in world1.

pub fn core_1_pif_pms_constrain_world_1_fe(
    &self
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE_R

Bits 10:11 - Core1 access fe permission in world1.

pub fn core_1_pif_pms_constrain_world_1_rtc(
    &self
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RTC_R

Bits 14:15 - Core1 access rtc permission in world1.

pub fn core_1_pif_pms_constrain_world_1_io_mux(
    &self
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_R

Bits 16:17 - Core1 access io_mux permission in world1.

pub fn core_1_pif_pms_constrain_world_1_hinf(
    &self
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_HINF_R

Bits 20:21 - Core1 access hinf permission in world1.

pub fn core_1_pif_pms_constrain_world_1_misc(
    &self
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_MISC_R

Bits 24:25 - Core1 access misc permission in world1.

pub fn core_1_pif_pms_constrain_world_1_i2c(
    &self
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_R

Bits 26:27 - Core1 access i2c permission in world1.

pub fn core_1_pif_pms_constrain_world_1_i2s0(
    &self
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S0_R

Bits 28:29 - Core1 access i2s0 permission in world1.

pub fn core_1_pif_pms_constrain_world_1_uart1(
    &self
) -> CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART1_R

Bits 30:31 - Core1 access uart1 permission in world1.

Methods from Deref<Target = R<CORE_1_PIF_PMS_CONSTRAIN_5_SPEC>>

pub fn bits(&self) -> REG::Ux

Reads raw bits from register.

Trait Implementations

impl Deref for R

type Target = R<CORE_1_PIF_PMS_CONSTRAIN_5_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &Self::Target

Dereferences the value.

impl From<R<CORE_1_PIF_PMS_CONSTRAIN_5_SPEC>> for R

fn from(reader: R<CORE_1_PIF_PMS_CONSTRAIN_5_SPEC>) -> Self

Converts to this type from the input type.