Struct esp32s3::rmt::ch_tx_conf0::W
source · pub struct W(_);
Expand description
Register CH%s_TX_CONF0
writer
Implementations§
source§impl W
impl W
sourcepub fn tx_start(&mut self) -> TX_START_W<'_, 0>
pub fn tx_start(&mut self) -> TX_START_W<'_, 0>
Bit 0 - Set this bit to start sending data on CHANNEL%s.
sourcepub fn mem_rd_rst(&mut self) -> MEM_RD_RST_W<'_, 1>
pub fn mem_rd_rst(&mut self) -> MEM_RD_RST_W<'_, 1>
Bit 1 - Set this bit to reset read ram address for CHANNEL%s by accessing transmitter.
sourcepub fn apb_mem_rst(&mut self) -> APB_MEM_RST_W<'_, 2>
pub fn apb_mem_rst(&mut self) -> APB_MEM_RST_W<'_, 2>
Bit 2 - Set this bit to reset W/R ram address for CHANNEL%s by accessing apb fifo.
sourcepub fn tx_conti_mode(&mut self) -> TX_CONTI_MODE_W<'_, 3>
pub fn tx_conti_mode(&mut self) -> TX_CONTI_MODE_W<'_, 3>
Bit 3 - Set this bit to restart transmission from the first data to the last data in CHANNEL%s.
sourcepub fn mem_tx_wrap_en(&mut self) -> MEM_TX_WRAP_EN_W<'_, 4>
pub fn mem_tx_wrap_en(&mut self) -> MEM_TX_WRAP_EN_W<'_, 4>
Bit 4 - This is the channel %s enable bit for wraparound mode: it will resume sending at the start when the data to be sent is more than its memory size.
sourcepub fn idle_out_lv(&mut self) -> IDLE_OUT_LV_W<'_, 5>
pub fn idle_out_lv(&mut self) -> IDLE_OUT_LV_W<'_, 5>
Bit 5 - This bit configures the level of output signal in CHANNEL%s when the latter is in IDLE state.
sourcepub fn idle_out_en(&mut self) -> IDLE_OUT_EN_W<'_, 6>
pub fn idle_out_en(&mut self) -> IDLE_OUT_EN_W<'_, 6>
Bit 6 - This is the output enable-control bit for CHANNEL%s in IDLE state.
sourcepub fn tx_stop(&mut self) -> TX_STOP_W<'_, 7>
pub fn tx_stop(&mut self) -> TX_STOP_W<'_, 7>
Bit 7 - Set this bit to stop the transmitter of CHANNEL%s sending data out.
sourcepub fn div_cnt(&mut self) -> DIV_CNT_W<'_, 8>
pub fn div_cnt(&mut self) -> DIV_CNT_W<'_, 8>
Bits 8:15 - This register is used to configure the divider for clock of CHANNEL%s.
sourcepub fn mem_size(&mut self) -> MEM_SIZE_W<'_, 16>
pub fn mem_size(&mut self) -> MEM_SIZE_W<'_, 16>
Bits 16:19 - This register is used to configure the maximum size of memory allocated to CHANNEL%s.
sourcepub fn carrier_eff_en(&mut self) -> CARRIER_EFF_EN_W<'_, 20>
pub fn carrier_eff_en(&mut self) -> CARRIER_EFF_EN_W<'_, 20>
Bit 20 - 1: Add carrier modulation on the output signal only at the send data state for CHANNEL%s. 0: Add carrier modulation on the output signal at all state for CHANNEL%s. Only valid when RMT_CARRIER_EN_CH%s is 1.
sourcepub fn carrier_en(&mut self) -> CARRIER_EN_W<'_, 21>
pub fn carrier_en(&mut self) -> CARRIER_EN_W<'_, 21>
Bit 21 - This is the carrier modulation enable-control bit for CHANNEL%s. 1: Add carrier modulation in the output signal. 0: No carrier modulation in sig_out.
sourcepub fn carrier_out_lv(&mut self) -> CARRIER_OUT_LV_W<'_, 22>
pub fn carrier_out_lv(&mut self) -> CARRIER_OUT_LV_W<'_, 22>
Bit 22 - This bit is used to configure the position of carrier wave for CHANNEL%s. 1’h0: add carrier wave on low level. 1’h1: add carrier wave on high level.
sourcepub fn afifo_rst(&mut self) -> AFIFO_RST_W<'_, 23>
pub fn afifo_rst(&mut self) -> AFIFO_RST_W<'_, 23>
Bit 23 - Reserved
sourcepub fn conf_update(&mut self) -> CONF_UPDATE_W<'_, 24>
pub fn conf_update(&mut self) -> CONF_UPDATE_W<'_, 24>
Bit 24 - synchronization bit for CHANNEL%s