Struct esp32s3::spi1::cache_fctrl::W

pub struct W(_);

Register CACHE_FCTRL writer

Implementations

impl W

pub fn cache_usr_cmd_4byte(&mut self) -> CACHE_USR_CMD_4BYTE_W<'_, 1>

Bit 1 - Set this bit to enable SPI1 transfer with 32 bits address. The value of SPI_MEM_USR_ADDR_BITLEN should be 31.

pub fn fdin_dual(&mut self) -> FDIN_DUAL_W<'_, 3>

Bit 3 - When SPI1 accesses to flash or Ext_RAM, set this bit to enable 2-bm in DIN phase.

pub fn fdout_dual(&mut self) -> FDOUT_DUAL_W<'_, 4>

Bit 4 - When SPI1 accesses to flash or Ext_RAM, set this bit to enable 2-bm in DOUT phase.

pub fn faddr_dual(&mut self) -> FADDR_DUAL_W<'_, 5>

Bit 5 - When SPI1 accesses to flash or Ext_RAM, set this bit to enable 2-bm in ADDR phase.

pub fn fdin_quad(&mut self) -> FDIN_QUAD_W<'_, 6>

Bit 6 - When SPI1 accesses to flash or Ext_RAM, set this bit to enable 4-bm in DIN phase.

pub fn fdout_quad(&mut self) -> FDOUT_QUAD_W<'_, 7>

Bit 7 - When SPI1 accesses to flash or Ext_RAM, set this bit to enable 4-bm in DOUT phase.

pub fn faddr_quad(&mut self) -> FADDR_QUAD_W<'_, 8>

Bit 8 - When SPI1 accesses to flash or Ext_RAM, set this bit to enable 4-bm in ADDR phase.

pub unsafe fn bits(&mut self, bits: u32) -> &mut Self

Writes raw bits to the register.

Methods from Deref<Target = W<CACHE_FCTRL_SPEC>>

pub unsafe fn bits(&mut self, bits: REG::Ux) -> &mut Self

Writes raw bits to the register.

Safety

Read datasheet or reference manual to find what values are allowed to pass.

Trait Implementations

impl Deref for W

type Target = W<CACHE_FCTRL_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &Self::Target

Dereferences the value.

impl DerefMut for W

fn deref_mut(&mut self) -> &mut Self::Target

Mutably dereferences the value.

impl From<W<CACHE_FCTRL_SPEC>> for W

fn from(writer: W<CACHE_FCTRL_SPEC>) -> Self

Converts to this type from the input type.