1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
#[doc = "Register `INT_CLR` writer"]
pub struct W(crate::W<INT_CLR_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<INT_CLR_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<INT_CLR_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<INT_CLR_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `CH_TX_END_INT_CLR[0-3]` writer - Set this bit to clear theCH%s_TX_END_INT interrupt."]
pub type CH_TX_END_INT_CLR_W<'a, const O: u8> = crate::BitWriter<'a, u32, INT_CLR_SPEC, bool, O>;
#[doc = "Field `CH_TX_ERR_INT_CLR[0-3]` writer - Set this bit to clear theCH%s_ERR_INT interrupt."]
pub type CH_TX_ERR_INT_CLR_W<'a, const O: u8> = crate::BitWriter<'a, u32, INT_CLR_SPEC, bool, O>;
#[doc = "Field `CH_TX_THR_EVENT_INT_CLR[0-3]` writer - Set this bit to clear theCH%s_TX_THR_EVENT_INT interrupt."]
pub type CH_TX_THR_EVENT_INT_CLR_W<'a, const O: u8> =
crate::BitWriter<'a, u32, INT_CLR_SPEC, bool, O>;
#[doc = "Field `CH_TX_LOOP_INT_CLR[0-3]` writer - Set this bit to clear theCH%s_TX_LOOP_INT interrupt."]
pub type CH_TX_LOOP_INT_CLR_W<'a, const O: u8> = crate::BitWriter<'a, u32, INT_CLR_SPEC, bool, O>;
#[doc = "Field `CH_RX_END_INT_CLR[4-7]` writer - Set this bit to clear theCH4_RX_END_INT interrupt."]
pub type CH_RX_END_INT_CLR_W<'a, const O: u8> = crate::BitWriter<'a, u32, INT_CLR_SPEC, bool, O>;
#[doc = "Field `CH_RX_ERR_INT_CLR[RX_CH4,RX_CH5,RX_CH6,RX_CH7]` writer - Set this bit to clear theCH4_ERR_INT interrupt."]
pub type CH_RX_ERR_INT_CLR_W<'a, const O: u8> = crate::BitWriter<'a, u32, INT_CLR_SPEC, bool, O>;
#[doc = "Field `CH4_RX_THR_EVENT_INT_CLR` writer - Set this bit to clear theCH4_RX_THR_EVENT_INT interrupt."]
pub type CH4_RX_THR_EVENT_INT_CLR_W<'a, const O: u8> =
crate::BitWriter<'a, u32, INT_CLR_SPEC, bool, O>;
#[doc = "Field `CH5_RX_THR_EVENT_INT_CLR` writer - Set this bit to clear theCH5_RX_THR_EVENT_INT interrupt."]
pub type CH5_RX_THR_EVENT_INT_CLR_W<'a, const O: u8> =
crate::BitWriter<'a, u32, INT_CLR_SPEC, bool, O>;
#[doc = "Field `CH6_RX_THR_EVENT_INT_CLR` writer - Set this bit to clear theCH6_RX_THR_EVENT_INT interrupt."]
pub type CH6_RX_THR_EVENT_INT_CLR_W<'a, const O: u8> =
crate::BitWriter<'a, u32, INT_CLR_SPEC, bool, O>;
#[doc = "Field `CH7_RX_THR_EVENT_INT_CLR` writer - Set this bit to clear theCH7_RX_THR_EVENT_INT interrupt."]
pub type CH7_RX_THR_EVENT_INT_CLR_W<'a, const O: u8> =
crate::BitWriter<'a, u32, INT_CLR_SPEC, bool, O>;
#[doc = "Field `TX_CH3_DMA_ACCESS_FAIL_INT_CLR` writer - Set this bit to clear the CH3_DMA_ACCESS_FAIL_INT interrupt."]
pub type TX_CH3_DMA_ACCESS_FAIL_INT_CLR_W<'a, const O: u8> =
crate::BitWriter<'a, u32, INT_CLR_SPEC, bool, O>;
#[doc = "Field `RX_CH7_DMA_ACCESS_FAIL_INT_CLR` writer - Set this bit to clear the CH7_DMA_ACCESS_FAIL_INT interrupt."]
pub type RX_CH7_DMA_ACCESS_FAIL_INT_CLR_W<'a, const O: u8> =
crate::BitWriter<'a, u32, INT_CLR_SPEC, bool, O>;
impl W {
#[doc = "Set this bit to clear theCH[0-3]_TX_END_INT interrupt."]
#[inline(always)]
#[must_use]
pub unsafe fn ch_tx_end_int_clr<const O: u8>(&mut self) -> CH_TX_END_INT_CLR_W<O> {
CH_TX_END_INT_CLR_W::new(self)
}
#[doc = "Bit 0 - Set this bit to clear theCH0_TX_END_INT interrupt."]
#[inline(always)]
#[must_use]
pub fn ch0_tx_end_int_clr(&mut self) -> CH_TX_END_INT_CLR_W<0> {
CH_TX_END_INT_CLR_W::new(self)
}
#[doc = "Bit 1 - Set this bit to clear theCH1_TX_END_INT interrupt."]
#[inline(always)]
#[must_use]
pub fn ch1_tx_end_int_clr(&mut self) -> CH_TX_END_INT_CLR_W<1> {
CH_TX_END_INT_CLR_W::new(self)
}
#[doc = "Bit 2 - Set this bit to clear theCH2_TX_END_INT interrupt."]
#[inline(always)]
#[must_use]
pub fn ch2_tx_end_int_clr(&mut self) -> CH_TX_END_INT_CLR_W<2> {
CH_TX_END_INT_CLR_W::new(self)
}
#[doc = "Bit 3 - Set this bit to clear theCH3_TX_END_INT interrupt."]
#[inline(always)]
#[must_use]
pub fn ch3_tx_end_int_clr(&mut self) -> CH_TX_END_INT_CLR_W<3> {
CH_TX_END_INT_CLR_W::new(self)
}
#[doc = "Set this bit to clear theCH[0-3]_ERR_INT interrupt."]
#[inline(always)]
#[must_use]
pub unsafe fn ch_tx_err_int_clr<const O: u8>(&mut self) -> CH_TX_ERR_INT_CLR_W<O> {
CH_TX_ERR_INT_CLR_W::new(self)
}
#[doc = "Bit 4 - Set this bit to clear theCH0_ERR_INT interrupt."]
#[inline(always)]
#[must_use]
pub fn ch0_tx_err_int_clr(&mut self) -> CH_TX_ERR_INT_CLR_W<4> {
CH_TX_ERR_INT_CLR_W::new(self)
}
#[doc = "Bit 5 - Set this bit to clear theCH1_ERR_INT interrupt."]
#[inline(always)]
#[must_use]
pub fn ch1_tx_err_int_clr(&mut self) -> CH_TX_ERR_INT_CLR_W<5> {
CH_TX_ERR_INT_CLR_W::new(self)
}
#[doc = "Bit 6 - Set this bit to clear theCH2_ERR_INT interrupt."]
#[inline(always)]
#[must_use]
pub fn ch2_tx_err_int_clr(&mut self) -> CH_TX_ERR_INT_CLR_W<6> {
CH_TX_ERR_INT_CLR_W::new(self)
}
#[doc = "Bit 7 - Set this bit to clear theCH3_ERR_INT interrupt."]
#[inline(always)]
#[must_use]
pub fn ch3_tx_err_int_clr(&mut self) -> CH_TX_ERR_INT_CLR_W<7> {
CH_TX_ERR_INT_CLR_W::new(self)
}
#[doc = "Set this bit to clear theCH[0-3]_TX_THR_EVENT_INT interrupt."]
#[inline(always)]
#[must_use]
pub unsafe fn ch_tx_thr_event_int_clr<const O: u8>(&mut self) -> CH_TX_THR_EVENT_INT_CLR_W<O> {
CH_TX_THR_EVENT_INT_CLR_W::new(self)
}
#[doc = "Bit 8 - Set this bit to clear theCH0_TX_THR_EVENT_INT interrupt."]
#[inline(always)]
#[must_use]
pub fn ch0_tx_thr_event_int_clr(&mut self) -> CH_TX_THR_EVENT_INT_CLR_W<8> {
CH_TX_THR_EVENT_INT_CLR_W::new(self)
}
#[doc = "Bit 9 - Set this bit to clear theCH1_TX_THR_EVENT_INT interrupt."]
#[inline(always)]
#[must_use]
pub fn ch1_tx_thr_event_int_clr(&mut self) -> CH_TX_THR_EVENT_INT_CLR_W<9> {
CH_TX_THR_EVENT_INT_CLR_W::new(self)
}
#[doc = "Bit 10 - Set this bit to clear theCH2_TX_THR_EVENT_INT interrupt."]
#[inline(always)]
#[must_use]
pub fn ch2_tx_thr_event_int_clr(&mut self) -> CH_TX_THR_EVENT_INT_CLR_W<10> {
CH_TX_THR_EVENT_INT_CLR_W::new(self)
}
#[doc = "Bit 11 - Set this bit to clear theCH3_TX_THR_EVENT_INT interrupt."]
#[inline(always)]
#[must_use]
pub fn ch3_tx_thr_event_int_clr(&mut self) -> CH_TX_THR_EVENT_INT_CLR_W<11> {
CH_TX_THR_EVENT_INT_CLR_W::new(self)
}
#[doc = "Set this bit to clear theCH[0-3]_TX_LOOP_INT interrupt."]
#[inline(always)]
#[must_use]
pub unsafe fn ch_tx_loop_int_clr<const O: u8>(&mut self) -> CH_TX_LOOP_INT_CLR_W<O> {
CH_TX_LOOP_INT_CLR_W::new(self)
}
#[doc = "Bit 12 - Set this bit to clear theCH0_TX_LOOP_INT interrupt."]
#[inline(always)]
#[must_use]
pub fn ch0_tx_loop_int_clr(&mut self) -> CH_TX_LOOP_INT_CLR_W<12> {
CH_TX_LOOP_INT_CLR_W::new(self)
}
#[doc = "Bit 13 - Set this bit to clear theCH1_TX_LOOP_INT interrupt."]
#[inline(always)]
#[must_use]
pub fn ch1_tx_loop_int_clr(&mut self) -> CH_TX_LOOP_INT_CLR_W<13> {
CH_TX_LOOP_INT_CLR_W::new(self)
}
#[doc = "Bit 14 - Set this bit to clear theCH2_TX_LOOP_INT interrupt."]
#[inline(always)]
#[must_use]
pub fn ch2_tx_loop_int_clr(&mut self) -> CH_TX_LOOP_INT_CLR_W<14> {
CH_TX_LOOP_INT_CLR_W::new(self)
}
#[doc = "Bit 15 - Set this bit to clear theCH3_TX_LOOP_INT interrupt."]
#[inline(always)]
#[must_use]
pub fn ch3_tx_loop_int_clr(&mut self) -> CH_TX_LOOP_INT_CLR_W<15> {
CH_TX_LOOP_INT_CLR_W::new(self)
}
#[doc = "Set this bit to clear theCH4_RX_END_INT interrupt."]
#[inline(always)]
#[must_use]
pub unsafe fn ch_rx_end_int_clr<const O: u8>(&mut self) -> CH_RX_END_INT_CLR_W<O> {
CH_RX_END_INT_CLR_W::new(self)
}
#[doc = "Bit 16 - Set this bit to clear theCH4_RX_END_INT interrupt."]
#[inline(always)]
#[must_use]
pub fn ch4_rx_end_int_clr(&mut self) -> CH_RX_END_INT_CLR_W<16> {
CH_RX_END_INT_CLR_W::new(self)
}
#[doc = "Bit 17 - Set this bit to clear theCH4_RX_END_INT interrupt."]
#[inline(always)]
#[must_use]
pub fn ch5_rx_end_int_clr(&mut self) -> CH_RX_END_INT_CLR_W<17> {
CH_RX_END_INT_CLR_W::new(self)
}
#[doc = "Bit 18 - Set this bit to clear theCH4_RX_END_INT interrupt."]
#[inline(always)]
#[must_use]
pub fn ch6_rx_end_int_clr(&mut self) -> CH_RX_END_INT_CLR_W<18> {
CH_RX_END_INT_CLR_W::new(self)
}
#[doc = "Bit 19 - Set this bit to clear theCH4_RX_END_INT interrupt."]
#[inline(always)]
#[must_use]
pub fn ch7_rx_end_int_clr(&mut self) -> CH_RX_END_INT_CLR_W<19> {
CH_RX_END_INT_CLR_W::new(self)
}
#[doc = "Set this bit to clear theCH4_ERR_INT interrupt."]
#[inline(always)]
#[must_use]
pub unsafe fn ch_rx_err_int_clr<const O: u8>(&mut self) -> CH_RX_ERR_INT_CLR_W<O> {
CH_RX_ERR_INT_CLR_W::new(self)
}
#[doc = "Bit 20 - Set this bit to clear theCH4_ERR_INT interrupt."]
#[inline(always)]
#[must_use]
pub fn chrx_ch4_rx_err_int_clr(&mut self) -> CH_RX_ERR_INT_CLR_W<20> {
CH_RX_ERR_INT_CLR_W::new(self)
}
#[doc = "Bit 21 - Set this bit to clear theCH4_ERR_INT interrupt."]
#[inline(always)]
#[must_use]
pub fn chrx_ch5_rx_err_int_clr(&mut self) -> CH_RX_ERR_INT_CLR_W<21> {
CH_RX_ERR_INT_CLR_W::new(self)
}
#[doc = "Bit 22 - Set this bit to clear theCH4_ERR_INT interrupt."]
#[inline(always)]
#[must_use]
pub fn chrx_ch6_rx_err_int_clr(&mut self) -> CH_RX_ERR_INT_CLR_W<22> {
CH_RX_ERR_INT_CLR_W::new(self)
}
#[doc = "Bit 23 - Set this bit to clear theCH4_ERR_INT interrupt."]
#[inline(always)]
#[must_use]
pub fn chrx_ch7_rx_err_int_clr(&mut self) -> CH_RX_ERR_INT_CLR_W<23> {
CH_RX_ERR_INT_CLR_W::new(self)
}
#[doc = "Bit 24 - Set this bit to clear theCH4_RX_THR_EVENT_INT interrupt."]
#[inline(always)]
#[must_use]
pub fn ch4_rx_thr_event_int_clr(&mut self) -> CH4_RX_THR_EVENT_INT_CLR_W<24> {
CH4_RX_THR_EVENT_INT_CLR_W::new(self)
}
#[doc = "Bit 25 - Set this bit to clear theCH5_RX_THR_EVENT_INT interrupt."]
#[inline(always)]
#[must_use]
pub fn ch5_rx_thr_event_int_clr(&mut self) -> CH5_RX_THR_EVENT_INT_CLR_W<25> {
CH5_RX_THR_EVENT_INT_CLR_W::new(self)
}
#[doc = "Bit 26 - Set this bit to clear theCH6_RX_THR_EVENT_INT interrupt."]
#[inline(always)]
#[must_use]
pub fn ch6_rx_thr_event_int_clr(&mut self) -> CH6_RX_THR_EVENT_INT_CLR_W<26> {
CH6_RX_THR_EVENT_INT_CLR_W::new(self)
}
#[doc = "Bit 27 - Set this bit to clear theCH7_RX_THR_EVENT_INT interrupt."]
#[inline(always)]
#[must_use]
pub fn ch7_rx_thr_event_int_clr(&mut self) -> CH7_RX_THR_EVENT_INT_CLR_W<27> {
CH7_RX_THR_EVENT_INT_CLR_W::new(self)
}
#[doc = "Bit 28 - Set this bit to clear the CH3_DMA_ACCESS_FAIL_INT interrupt."]
#[inline(always)]
#[must_use]
pub fn tx_ch3_dma_access_fail_int_clr(&mut self) -> TX_CH3_DMA_ACCESS_FAIL_INT_CLR_W<28> {
TX_CH3_DMA_ACCESS_FAIL_INT_CLR_W::new(self)
}
#[doc = "Bit 29 - Set this bit to clear the CH7_DMA_ACCESS_FAIL_INT interrupt."]
#[inline(always)]
#[must_use]
pub fn rx_ch7_dma_access_fail_int_clr(&mut self) -> RX_CH7_DMA_ACCESS_FAIL_INT_CLR_W<29> {
RX_CH7_DMA_ACCESS_FAIL_INT_CLR_W::new(self)
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Interrupt clear bits\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [int_clr](index.html) module"]
pub struct INT_CLR_SPEC;
impl crate::RegisterSpec for INT_CLR_SPEC {
type Ux = u32;
}
#[doc = "`write(|w| ..)` method takes [int_clr::W](W) writer structure"]
impl crate::Writable for INT_CLR_SPEC {
type Writer = W;
const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
}
#[doc = "`reset()` method sets INT_CLR to value 0"]
impl crate::Resettable for INT_CLR_SPEC {
const RESET_VALUE: Self::Ux = 0;
}