Struct esp32s3::spi0::timing_cali::W

pub struct W(_);

Register TIMING_CALI writer

Implementations

impl W

pub fn timing_clk_ena(&mut self) -> TIMING_CLK_ENA_W<'_, 0>

Bit 0 - Set this bit to power on HCLK. When PLL is powered on, the frequency of HCLK equals to that of PLL. Otherwise, the frequency equals to that of XTAL.

pub fn timing_cali(&mut self) -> TIMING_CALI_W<'_, 1>

Bit 1 - Set this bit to add extra SPI_CLK cycles in DUMMY phase for all reading operations.

pub fn extra_dummy_cyclelen(&mut self) -> EXTRA_DUMMY_CYCLELEN_W<'_, 2>

Bits 2:4 - Extra SPI_CLK cycles added in DUMMY phase for timing compensation, when SPI0 accesses to flash. Active when SPI_MEM_TIMING_CALI bit is set.

pub unsafe fn bits(&mut self, bits: u32) -> &mut Self

Writes raw bits to the register.

Methods from Deref<Target = W<TIMING_CALI_SPEC>>

pub unsafe fn bits(&mut self, bits: REG::Ux) -> &mut Self

Writes raw bits to the register.

Safety

Read datasheet or reference manual to find what values are allowed to pass.

Trait Implementations

impl Deref for W

type Target = W<TIMING_CALI_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &Self::Target

Dereferences the value.

impl DerefMut for W

fn deref_mut(&mut self) -> &mut Self::Target

Mutably dereferences the value.

impl From<W<TIMING_CALI_SPEC>> for W

fn from(writer: W<TIMING_CALI_SPEC>) -> Self

Converts to this type from the input type.