Struct esp32s3::rtc_cntl::cocpu_ctrl::W
source · pub struct W(_);
Expand description
Register COCPU_CTRL
writer
Implementations§
source§impl W
impl W
sourcepub fn cocpu_clk_fo(&mut self) -> COCPU_CLK_FO_W<'_, 0>
pub fn cocpu_clk_fo(&mut self) -> COCPU_CLK_FO_W<'_, 0>
Bit 0 - cocpu clk force on
sourcepub fn cocpu_start_2_reset_dis(&mut self) -> COCPU_START_2_RESET_DIS_W<'_, 1>
pub fn cocpu_start_2_reset_dis(&mut self) -> COCPU_START_2_RESET_DIS_W<'_, 1>
Bits 1:6 - time from start cocpu to pull down reset
sourcepub fn cocpu_start_2_intr_en(&mut self) -> COCPU_START_2_INTR_EN_W<'_, 7>
pub fn cocpu_start_2_intr_en(&mut self) -> COCPU_START_2_INTR_EN_W<'_, 7>
Bits 7:12 - time from start cocpu to give start interrupt
sourcepub fn cocpu_shut(&mut self) -> COCPU_SHUT_W<'_, 13>
pub fn cocpu_shut(&mut self) -> COCPU_SHUT_W<'_, 13>
Bit 13 - to shut cocpu
sourcepub fn cocpu_shut_2_clk_dis(&mut self) -> COCPU_SHUT_2_CLK_DIS_W<'_, 14>
pub fn cocpu_shut_2_clk_dis(&mut self) -> COCPU_SHUT_2_CLK_DIS_W<'_, 14>
Bits 14:21 - time from shut cocpu to disable clk
sourcepub fn cocpu_shut_reset_en(&mut self) -> COCPU_SHUT_RESET_EN_W<'_, 22>
pub fn cocpu_shut_reset_en(&mut self) -> COCPU_SHUT_RESET_EN_W<'_, 22>
Bit 22 - to reset cocpu
sourcepub fn cocpu_sel(&mut self) -> COCPU_SEL_W<'_, 23>
pub fn cocpu_sel(&mut self) -> COCPU_SEL_W<'_, 23>
Bit 23 - 1: old ULP 0: new riscV
sourcepub fn cocpu_done_force(&mut self) -> COCPU_DONE_FORCE_W<'_, 24>
pub fn cocpu_done_force(&mut self) -> COCPU_DONE_FORCE_W<'_, 24>
Bit 24 - 1: select riscv done 0: select ulp done
sourcepub fn cocpu_done(&mut self) -> COCPU_DONE_W<'_, 25>
pub fn cocpu_done(&mut self) -> COCPU_DONE_W<'_, 25>
Bit 25 - done signal used by riscv to control timer.
sourcepub fn cocpu_sw_int_trigger(&mut self) -> COCPU_SW_INT_TRIGGER_W<'_, 26>
pub fn cocpu_sw_int_trigger(&mut self) -> COCPU_SW_INT_TRIGGER_W<'_, 26>
Bit 26 - trigger cocpu register interrupt
sourcepub fn cocpu_clkgate_en(&mut self) -> COCPU_CLKGATE_EN_W<'_, 27>
pub fn cocpu_clkgate_en(&mut self) -> COCPU_CLKGATE_EN_W<'_, 27>
Bit 27 - open ulp-riscv clk gate