Struct esp32s3::extmem::icache_ctrl::R

pub struct R(_);

Register ICACHE_CTRL reader

Implementations

impl R

pub fn icache_enable(&self) -> ICACHE_ENABLE_R

Bit 0 - The bit is used to activate the data cache. 0: disable, 1: enable

pub fn icache_way_mode(&self) -> ICACHE_WAY_MODE_R

Bit 1 - The bit is used to configure cache way mode.0: 4-way, 1: 8-way

pub fn icache_size_mode(&self) -> ICACHE_SIZE_MODE_R

Bit 2 - The bit is used to configure cache memory size.0: 16KB, 1: 32KB

pub fn icache_blocksize_mode(&self) -> ICACHE_BLOCKSIZE_MODE_R

Bit 3 - The bit is used to configure cache block size.0: 16 bytes, 1: 32 bytes

Methods from Deref<Target = R<ICACHE_CTRL_SPEC>>

pub fn bits(&self) -> REG::Ux

Reads raw bits from register.

Trait Implementations

impl Deref for R

type Target = R<ICACHE_CTRL_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &Self::Target

Dereferences the value.

impl From<R<ICACHE_CTRL_SPEC>> for R

fn from(reader: R<ICACHE_CTRL_SPEC>) -> Self

Converts to this type from the input type.