Struct esp32s3::debug_assist::core_0_interrupt_rls::W

pub struct W(_);

Register CORE_0_INTERRUPT_RLS writer

Implementations

impl W

pub fn core_0_area_dram0_0_rd_rls(
    &mut self
) -> CORE_0_AREA_DRAM0_0_RD_RLS_W<'_, 0>

Bit 0 - Core0 dram0 area0 read monitor interrupt enable

pub fn core_0_area_dram0_0_wr_rls(
    &mut self
) -> CORE_0_AREA_DRAM0_0_WR_RLS_W<'_, 1>

Bit 1 - Core0 dram0 area0 write monitor interrupt enable

pub fn core_0_area_dram0_1_rd_rls(
    &mut self
) -> CORE_0_AREA_DRAM0_1_RD_RLS_W<'_, 2>

Bit 2 - Core0 dram0 area1 read monitor interrupt enable

pub fn core_0_area_dram0_1_wr_rls(
    &mut self
) -> CORE_0_AREA_DRAM0_1_WR_RLS_W<'_, 3>

Bit 3 - Core0 dram0 area1 write monitor interrupt enable

pub fn core_0_area_pif_0_rd_rls(&mut self) -> CORE_0_AREA_PIF_0_RD_RLS_W<'_, 4>

Bit 4 - Core0 PIF area0 read monitor interrupt enable

pub fn core_0_area_pif_0_wr_rls(&mut self) -> CORE_0_AREA_PIF_0_WR_RLS_W<'_, 5>

Bit 5 - Core0 PIF area0 write monitor interrupt enable

pub fn core_0_area_pif_1_rd_rls(&mut self) -> CORE_0_AREA_PIF_1_RD_RLS_W<'_, 6>

Bit 6 - Core0 PIF area1 read monitor interrupt enable

pub fn core_0_area_pif_1_wr_rls(&mut self) -> CORE_0_AREA_PIF_1_WR_RLS_W<'_, 7>

Bit 7 - Core0 PIF area1 write monitor interrupt enable

pub fn core_0_sp_spill_min_rls(&mut self) -> CORE_0_SP_SPILL_MIN_RLS_W<'_, 8>

Bit 8 - Core0 stackpoint overflow monitor interrupt enable

pub fn core_0_sp_spill_max_rls(&mut self) -> CORE_0_SP_SPILL_MAX_RLS_W<'_, 9>

Bit 9 - Core0 stackpoint underflow monitor interrupt enable

pub fn core_0_iram0_exception_monitor_rls(
    &mut self
) -> CORE_0_IRAM0_EXCEPTION_MONITOR_RLS_W<'_, 10>

Bit 10 - IBUS busy monitor interrupt enable

pub fn core_0_dram0_exception_monitor_rls(
    &mut self
) -> CORE_0_DRAM0_EXCEPTION_MONITOR_RLS_W<'_, 11>

Bit 11 - DBUS busy monitor interrupt enbale

pub unsafe fn bits(&mut self, bits: u32) -> &mut Self

Writes raw bits to the register.

Methods from Deref<Target = W<CORE_0_INTERRUPT_RLS_SPEC>>

pub unsafe fn bits(&mut self, bits: REG::Ux) -> &mut Self

Writes raw bits to the register.

Safety

Read datasheet or reference manual to find what values are allowed to pass.

Trait Implementations

impl Deref for W

type Target = W<CORE_0_INTERRUPT_RLS_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &Self::Target

Dereferences the value.

impl DerefMut for W

fn deref_mut(&mut self) -> &mut Self::Target

Mutably dereferences the value.

impl From<W<CORE_0_INTERRUPT_RLS_SPEC>> for W

fn from(writer: W<CORE_0_INTERRUPT_RLS_SPEC>) -> Self

Converts to this type from the input type.