Struct esp32s3::extmem::RegisterBlock

source ·

#[repr(C)]
pub struct RegisterBlock {Show 95 fields
    pub dcache_ctrl: DCACHE_CTRL,
    pub dcache_ctrl1: DCACHE_CTRL1,
    pub dcache_tag_power_ctrl: DCACHE_TAG_POWER_CTRL,
    pub dcache_prelock_ctrl: DCACHE_PRELOCK_CTRL,
    pub dcache_prelock_sct0_addr: DCACHE_PRELOCK_SCT0_ADDR,
    pub dcache_prelock_sct1_addr: DCACHE_PRELOCK_SCT1_ADDR,
    pub dcache_prelock_sct_size: DCACHE_PRELOCK_SCT_SIZE,
    pub dcache_lock_ctrl: DCACHE_LOCK_CTRL,
    pub dcache_lock_addr: DCACHE_LOCK_ADDR,
    pub dcache_lock_size: DCACHE_LOCK_SIZE,
    pub dcache_sync_ctrl: DCACHE_SYNC_CTRL,
    pub dcache_sync_addr: DCACHE_SYNC_ADDR,
    pub dcache_sync_size: DCACHE_SYNC_SIZE,
    pub dcache_occupy_ctrl: DCACHE_OCCUPY_CTRL,
    pub dcache_occupy_addr: DCACHE_OCCUPY_ADDR,
    pub dcache_occupy_size: DCACHE_OCCUPY_SIZE,
    pub dcache_preload_ctrl: DCACHE_PRELOAD_CTRL,
    pub dcache_preload_addr: DCACHE_PRELOAD_ADDR,
    pub dcache_preload_size: DCACHE_PRELOAD_SIZE,
    pub dcache_autoload_ctrl: DCACHE_AUTOLOAD_CTRL,
    pub dcache_autoload_sct0_addr: DCACHE_AUTOLOAD_SCT0_ADDR,
    pub dcache_autoload_sct0_size: DCACHE_AUTOLOAD_SCT0_SIZE,
    pub dcache_autoload_sct1_addr: DCACHE_AUTOLOAD_SCT1_ADDR,
    pub dcache_autoload_sct1_size: DCACHE_AUTOLOAD_SCT1_SIZE,
    pub icache_ctrl: ICACHE_CTRL,
    pub icache_ctrl1: ICACHE_CTRL1,
    pub icache_tag_power_ctrl: ICACHE_TAG_POWER_CTRL,
    pub icache_prelock_ctrl: ICACHE_PRELOCK_CTRL,
    pub icache_prelock_sct0_addr: ICACHE_PRELOCK_SCT0_ADDR,
    pub icache_prelock_sct1_addr: ICACHE_PRELOCK_SCT1_ADDR,
    pub icache_prelock_sct_size: ICACHE_PRELOCK_SCT_SIZE,
    pub icache_lock_ctrl: ICACHE_LOCK_CTRL,
    pub icache_lock_addr: ICACHE_LOCK_ADDR,
    pub icache_lock_size: ICACHE_LOCK_SIZE,
    pub icache_sync_ctrl: ICACHE_SYNC_CTRL,
    pub icache_sync_addr: ICACHE_SYNC_ADDR,
    pub icache_sync_size: ICACHE_SYNC_SIZE,
    pub icache_preload_ctrl: ICACHE_PRELOAD_CTRL,
    pub icache_preload_addr: ICACHE_PRELOAD_ADDR,
    pub icache_preload_size: ICACHE_PRELOAD_SIZE,
    pub icache_autoload_ctrl: ICACHE_AUTOLOAD_CTRL,
    pub icache_autoload_sct0_addr: ICACHE_AUTOLOAD_SCT0_ADDR,
    pub icache_autoload_sct0_size: ICACHE_AUTOLOAD_SCT0_SIZE,
    pub icache_autoload_sct1_addr: ICACHE_AUTOLOAD_SCT1_ADDR,
    pub icache_autoload_sct1_size: ICACHE_AUTOLOAD_SCT1_SIZE,
    pub ibus_to_flash_start_vaddr: IBUS_TO_FLASH_START_VADDR,
    pub ibus_to_flash_end_vaddr: IBUS_TO_FLASH_END_VADDR,
    pub dbus_to_flash_start_vaddr: DBUS_TO_FLASH_START_VADDR,
    pub dbus_to_flash_end_vaddr: DBUS_TO_FLASH_END_VADDR,
    pub cache_acs_cnt_clr: CACHE_ACS_CNT_CLR,
    pub ibus_acs_miss_cnt: IBUS_ACS_MISS_CNT,
    pub ibus_acs_cnt: IBUS_ACS_CNT,
    pub dbus_acs_flash_miss_cnt: DBUS_ACS_FLASH_MISS_CNT,
    pub dbus_acs_spiram_miss_cnt: DBUS_ACS_SPIRAM_MISS_CNT,
    pub dbus_acs_cnt: DBUS_ACS_CNT,
    pub cache_ilg_int_ena: CACHE_ILG_INT_ENA,
    pub cache_ilg_int_clr: CACHE_ILG_INT_CLR,
    pub cache_ilg_int_st: CACHE_ILG_INT_ST,
    pub core0_acs_cache_int_ena: CORE0_ACS_CACHE_INT_ENA,
    pub core0_acs_cache_int_clr: CORE0_ACS_CACHE_INT_CLR,
    pub core0_acs_cache_int_st: CORE0_ACS_CACHE_INT_ST,
    pub core1_acs_cache_int_ena: CORE1_ACS_CACHE_INT_ENA,
    pub core1_acs_cache_int_clr: CORE1_ACS_CACHE_INT_CLR,
    pub core1_acs_cache_int_st: CORE1_ACS_CACHE_INT_ST,
    pub core0_dbus_reject_st: CORE0_DBUS_REJECT_ST,
    pub core0_dbus_reject_vaddr: CORE0_DBUS_REJECT_VADDR,
    pub core0_ibus_reject_st: CORE0_IBUS_REJECT_ST,
    pub core0_ibus_reject_vaddr: CORE0_IBUS_REJECT_VADDR,
    pub core1_dbus_reject_st: CORE1_DBUS_REJECT_ST,
    pub core1_dbus_reject_vaddr: CORE1_DBUS_REJECT_VADDR,
    pub core1_ibus_reject_st: CORE1_IBUS_REJECT_ST,
    pub core1_ibus_reject_vaddr: CORE1_IBUS_REJECT_VADDR,
    pub cache_mmu_fault_content: CACHE_MMU_FAULT_CONTENT,
    pub cache_mmu_fault_vaddr: CACHE_MMU_FAULT_VADDR,
    pub cache_wrap_around_ctrl: CACHE_WRAP_AROUND_CTRL,
    pub cache_mmu_power_ctrl: CACHE_MMU_POWER_CTRL,
    pub cache_state: CACHE_STATE,
    pub cache_encrypt_decrypt_record_disable: CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE,
    pub cache_encrypt_decrypt_clk_force_on: CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON,
    pub cache_bridge_arbiter_ctrl: CACHE_BRIDGE_ARBITER_CTRL,
    pub cache_preload_int_ctrl: CACHE_PRELOAD_INT_CTRL,
    pub cache_sync_int_ctrl: CACHE_SYNC_INT_CTRL,
    pub cache_mmu_owner: CACHE_MMU_OWNER,
    pub cache_conf_misc: CACHE_CONF_MISC,
    pub dcache_freeze: DCACHE_FREEZE,
    pub icache_freeze: ICACHE_FREEZE,
    pub icache_atomic_operate_ena: ICACHE_ATOMIC_OPERATE_ENA,
    pub dcache_atomic_operate_ena: DCACHE_ATOMIC_OPERATE_ENA,
    pub cache_request: CACHE_REQUEST,
    pub clock_gate: CLOCK_GATE,
    pub cache_tag_object_ctrl: CACHE_TAG_OBJECT_CTRL,
    pub cache_tag_way_object: CACHE_TAG_WAY_OBJECT,
    pub cache_vaddr: CACHE_VADDR,
    pub cache_tag_content: CACHE_TAG_CONTENT,
    pub date: DATE,
    /* private fields */
}

Expand description

Register block

Fields§

§dcache_ctrl: DCACHE_CTRL

0x00 - ******* Description ***********

§dcache_ctrl1: DCACHE_CTRL1

0x04 - ******* Description ***********

§dcache_tag_power_ctrl: DCACHE_TAG_POWER_CTRL

0x08 - ******* Description ***********

§dcache_prelock_ctrl: DCACHE_PRELOCK_CTRL

0x0c - ******* Description ***********

§dcache_prelock_sct0_addr: DCACHE_PRELOCK_SCT0_ADDR

0x10 - ******* Description ***********

§dcache_prelock_sct1_addr: DCACHE_PRELOCK_SCT1_ADDR

0x14 - ******* Description ***********

§dcache_prelock_sct_size: DCACHE_PRELOCK_SCT_SIZE

0x18 - ******* Description ***********

§dcache_lock_ctrl: DCACHE_LOCK_CTRL

0x1c - ******* Description ***********

§dcache_lock_addr: DCACHE_LOCK_ADDR

0x20 - ******* Description ***********

§dcache_lock_size: DCACHE_LOCK_SIZE

0x24 - ******* Description ***********

§dcache_sync_ctrl: DCACHE_SYNC_CTRL

0x28 - ******* Description ***********

§dcache_sync_addr: DCACHE_SYNC_ADDR

0x2c - ******* Description ***********

§dcache_sync_size: DCACHE_SYNC_SIZE

0x30 - ******* Description ***********

§dcache_occupy_ctrl: DCACHE_OCCUPY_CTRL

0x34 - ******* Description ***********

§dcache_occupy_addr: DCACHE_OCCUPY_ADDR

0x38 - ******* Description ***********

§dcache_occupy_size: DCACHE_OCCUPY_SIZE

0x3c - ******* Description ***********

§dcache_preload_ctrl: DCACHE_PRELOAD_CTRL

0x40 - ******* Description ***********

§dcache_preload_addr: DCACHE_PRELOAD_ADDR

0x44 - ******* Description ***********

§dcache_preload_size: DCACHE_PRELOAD_SIZE

0x48 - ******* Description ***********

§dcache_autoload_ctrl: DCACHE_AUTOLOAD_CTRL

0x4c - ******* Description ***********

§dcache_autoload_sct0_addr: DCACHE_AUTOLOAD_SCT0_ADDR

0x50 - ******* Description ***********

§dcache_autoload_sct0_size: DCACHE_AUTOLOAD_SCT0_SIZE

0x54 - ******* Description ***********

§dcache_autoload_sct1_addr: DCACHE_AUTOLOAD_SCT1_ADDR

0x58 - ******* Description ***********

§dcache_autoload_sct1_size: DCACHE_AUTOLOAD_SCT1_SIZE

0x5c - ******* Description ***********

§icache_ctrl: ICACHE_CTRL

0x60 - ******* Description ***********

§icache_ctrl1: ICACHE_CTRL1

0x64 - ******* Description ***********

§icache_tag_power_ctrl: ICACHE_TAG_POWER_CTRL

0x68 - ******* Description ***********

§icache_prelock_ctrl: ICACHE_PRELOCK_CTRL

0x6c - ******* Description ***********

§icache_prelock_sct0_addr: ICACHE_PRELOCK_SCT0_ADDR

0x70 - ******* Description ***********

§icache_prelock_sct1_addr: ICACHE_PRELOCK_SCT1_ADDR

0x74 - ******* Description ***********

§icache_prelock_sct_size: ICACHE_PRELOCK_SCT_SIZE

0x78 - ******* Description ***********

§icache_lock_ctrl: ICACHE_LOCK_CTRL

0x7c - ******* Description ***********

§icache_lock_addr: ICACHE_LOCK_ADDR

0x80 - ******* Description ***********

§icache_lock_size: ICACHE_LOCK_SIZE

0x84 - ******* Description ***********

§icache_sync_ctrl: ICACHE_SYNC_CTRL

0x88 - ******* Description ***********

§icache_sync_addr: ICACHE_SYNC_ADDR

0x8c - ******* Description ***********

§icache_sync_size: ICACHE_SYNC_SIZE

0x90 - ******* Description ***********

§icache_preload_ctrl: ICACHE_PRELOAD_CTRL

0x94 - ******* Description ***********

§icache_preload_addr: ICACHE_PRELOAD_ADDR

0x98 - ******* Description ***********

§icache_preload_size: ICACHE_PRELOAD_SIZE

0x9c - ******* Description ***********

§icache_autoload_ctrl: ICACHE_AUTOLOAD_CTRL

0xa0 - ******* Description ***********

§icache_autoload_sct0_addr: ICACHE_AUTOLOAD_SCT0_ADDR

0xa4 - ******* Description ***********

§icache_autoload_sct0_size: ICACHE_AUTOLOAD_SCT0_SIZE

0xa8 - ******* Description ***********

§icache_autoload_sct1_addr: ICACHE_AUTOLOAD_SCT1_ADDR

0xac - ******* Description ***********

§icache_autoload_sct1_size: ICACHE_AUTOLOAD_SCT1_SIZE

0xb0 - ******* Description ***********

§ibus_to_flash_start_vaddr: IBUS_TO_FLASH_START_VADDR

0xb4 - ******* Description ***********

§ibus_to_flash_end_vaddr: IBUS_TO_FLASH_END_VADDR

0xb8 - ******* Description ***********

§dbus_to_flash_start_vaddr: DBUS_TO_FLASH_START_VADDR

0xbc - ******* Description ***********

§dbus_to_flash_end_vaddr: DBUS_TO_FLASH_END_VADDR

0xc0 - ******* Description ***********

§cache_acs_cnt_clr: CACHE_ACS_CNT_CLR

0xc4 - ******* Description ***********

§ibus_acs_miss_cnt: IBUS_ACS_MISS_CNT

0xc8 - ******* Description ***********

§ibus_acs_cnt: IBUS_ACS_CNT

0xcc - ******* Description ***********

§dbus_acs_flash_miss_cnt: DBUS_ACS_FLASH_MISS_CNT

0xd0 - ******* Description ***********

§dbus_acs_spiram_miss_cnt: DBUS_ACS_SPIRAM_MISS_CNT

0xd4 - ******* Description ***********

§dbus_acs_cnt: DBUS_ACS_CNT

0xd8 - ******* Description ***********

§cache_ilg_int_ena: CACHE_ILG_INT_ENA

0xdc - ******* Description ***********

§cache_ilg_int_clr: CACHE_ILG_INT_CLR

0xe0 - ******* Description ***********

§cache_ilg_int_st: CACHE_ILG_INT_ST

0xe4 - ******* Description ***********

§core0_acs_cache_int_ena: CORE0_ACS_CACHE_INT_ENA

0xe8 - ******* Description ***********

§core0_acs_cache_int_clr: CORE0_ACS_CACHE_INT_CLR

0xec - ******* Description ***********

§core0_acs_cache_int_st: CORE0_ACS_CACHE_INT_ST

0xf0 - ******* Description ***********

§core1_acs_cache_int_ena: CORE1_ACS_CACHE_INT_ENA

0xf4 - ******* Description ***********

§core1_acs_cache_int_clr: CORE1_ACS_CACHE_INT_CLR

0xf8 - ******* Description ***********

§core1_acs_cache_int_st: CORE1_ACS_CACHE_INT_ST

0xfc - ******* Description ***********

§core0_dbus_reject_st: CORE0_DBUS_REJECT_ST

0x100 - ******* Description ***********

§core0_dbus_reject_vaddr: CORE0_DBUS_REJECT_VADDR

0x104 - ******* Description ***********

§core0_ibus_reject_st: CORE0_IBUS_REJECT_ST

0x108 - ******* Description ***********

§core0_ibus_reject_vaddr: CORE0_IBUS_REJECT_VADDR

0x10c - ******* Description ***********

§core1_dbus_reject_st: CORE1_DBUS_REJECT_ST

0x110 - ******* Description ***********

§core1_dbus_reject_vaddr: CORE1_DBUS_REJECT_VADDR

0x114 - ******* Description ***********

§core1_ibus_reject_st: CORE1_IBUS_REJECT_ST

0x118 - ******* Description ***********

§core1_ibus_reject_vaddr: CORE1_IBUS_REJECT_VADDR

0x11c - ******* Description ***********

§cache_mmu_fault_content: CACHE_MMU_FAULT_CONTENT

0x120 - ******* Description ***********

§cache_mmu_fault_vaddr: CACHE_MMU_FAULT_VADDR

0x124 - ******* Description ***********

§cache_wrap_around_ctrl: CACHE_WRAP_AROUND_CTRL

0x128 - ******* Description ***********

§cache_mmu_power_ctrl: CACHE_MMU_POWER_CTRL

0x12c - ******* Description ***********

§cache_state: CACHE_STATE

0x130 - ******* Description ***********

§cache_encrypt_decrypt_record_disable: CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE

0x134 - ******* Description ***********

§cache_encrypt_decrypt_clk_force_on: CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON

0x138 - ******* Description ***********

§cache_bridge_arbiter_ctrl: CACHE_BRIDGE_ARBITER_CTRL

0x13c - ******* Description ***********

§cache_preload_int_ctrl: CACHE_PRELOAD_INT_CTRL

0x140 - ******* Description ***********

§cache_sync_int_ctrl: CACHE_SYNC_INT_CTRL

0x144 - ******* Description ***********

§cache_mmu_owner: CACHE_MMU_OWNER

0x148 - ******* Description ***********

§cache_conf_misc: CACHE_CONF_MISC

0x14c - ******* Description ***********

§dcache_freeze: DCACHE_FREEZE

0x150 - ******* Description ***********

§icache_freeze: ICACHE_FREEZE

0x154 - ******* Description ***********

§icache_atomic_operate_ena: ICACHE_ATOMIC_OPERATE_ENA

0x158 - ******* Description ***********

§dcache_atomic_operate_ena: DCACHE_ATOMIC_OPERATE_ENA

0x15c - ******* Description ***********

§cache_request: CACHE_REQUEST

0x160 - ******* Description ***********

§clock_gate: CLOCK_GATE

0x164 - ******* Description ***********

§cache_tag_object_ctrl: CACHE_TAG_OBJECT_CTRL

0x180 - ******* Description ***********

§cache_tag_way_object: CACHE_TAG_WAY_OBJECT

0x184 - ******* Description ***********

§cache_vaddr: CACHE_VADDR

0x188 - ******* Description ***********

§cache_tag_content: CACHE_TAG_CONTENT

0x18c - ******* Description ***********

§date: DATE

0x3fc - ******* Description ***********

Auto Trait Implementations§

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impl UnwindSafe for RegisterBlock

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Performs the conversion.

Struct esp32s3::extmem::RegisterBlock

Fields§

Auto Trait Implementations§

impl !RefUnwindSafe for RegisterBlock

impl Send for RegisterBlock

impl !Sync for RegisterBlock

impl Unpin for RegisterBlock

impl UnwindSafe for RegisterBlock

Blanket Implementations§

impl<T> Any for Twhere
T: 'static + ?Sized,

fn type_id(&self) -> TypeId

impl<T> Borrow<T> for Twhere
T: ?Sized,

fn borrow(&self) -> &T

impl<T> BorrowMut<T> for Twhere
T: ?Sized,

fn borrow_mut(&mut self) -> &mut T

impl<T> From<T> for T

fn from(t: T) -> T

impl<T, U> Into<U> for Twhere
U: From<T>,

fn into(self) -> U

impl<T, U> TryFrom<U> for Twhere
U: Into<T>,

type Error = Infallible

fn try_from(value: U) -> Result<T, <T as TryFrom<U>>::Error>

impl<T, U> TryInto<U> for Twhere
U: TryFrom<T>,

type Error = <U as TryFrom<T>>::Error

fn try_into(self) -> Result<U, <U as TryFrom<T>>::Error>

Struct esp32s3::extmem::RegisterBlock

Fields§

Auto Trait Implementations§

impl !RefUnwindSafe for RegisterBlock

impl Send for RegisterBlock

impl !Sync for RegisterBlock

impl Unpin for RegisterBlock

impl UnwindSafe for RegisterBlock

Blanket Implementations§

impl<T> Any for Twhere T: 'static + ?Sized,

fn type_id(&self) -> TypeId

impl<T> Borrow<T> for Twhere T: ?Sized,

fn borrow(&self) -> &T

impl<T> BorrowMut<T> for Twhere T: ?Sized,

fn borrow_mut(&mut self) -> &mut T

impl<T> From<T> for T

fn from(t: T) -> T

impl<T, U> Into<U> for Twhere U: From<T>,

fn into(self) -> U

impl<T, U> TryFrom<U> for Twhere U: Into<T>,

type Error = Infallible

fn try_from(value: U) -> Result<T, <T as TryFrom<U>>::Error>

impl<T, U> TryInto<U> for Twhere U: TryFrom<T>,

type Error = <U as TryFrom<T>>::Error

fn try_into(self) -> Result<U, <U as TryFrom<T>>::Error>

impl<T> Any for Twhere
T: 'static + ?Sized,

impl<T> Borrow<T> for Twhere
T: ?Sized,

impl<T> BorrowMut<T> for Twhere
T: ?Sized,

impl<T, U> Into<U> for Twhere
U: From<T>,

impl<T, U> TryFrom<U> for Twhere
U: Into<T>,

impl<T, U> TryInto<U> for Twhere
U: TryFrom<T>,