Struct esp32s3::rmt::int_ena::W

pub struct W(_);

Register INT_ENA writer

Implementations

impl W

pub unsafe fn ch_tx_end_int_ena<const O: u8>(
    &mut self
) -> CH_TX_END_INT_ENA_W<'_, O>

The interrupt enable bit for CH[0-3]_TX_END_INT.

pub fn ch0_tx_end_int_ena(&mut self) -> CH_TX_END_INT_ENA_W<'_, 0>

Bit 0 - The interrupt enable bit for CH0_TX_END_INT.

pub fn ch1_tx_end_int_ena(&mut self) -> CH_TX_END_INT_ENA_W<'_, 1>

Bit 1 - The interrupt enable bit for CH1_TX_END_INT.

pub fn ch2_tx_end_int_ena(&mut self) -> CH_TX_END_INT_ENA_W<'_, 2>

Bit 2 - The interrupt enable bit for CH2_TX_END_INT.

pub fn ch3_tx_end_int_ena(&mut self) -> CH_TX_END_INT_ENA_W<'_, 3>

Bit 3 - The interrupt enable bit for CH3_TX_END_INT.

pub unsafe fn ch_tx_err_int_ena<const O: u8>(
    &mut self
) -> CH_TX_ERR_INT_ENA_W<'_, O>

The interrupt enable bit for CH[0-3]_ERR_INT.

pub fn ch0_tx_err_int_ena(&mut self) -> CH_TX_ERR_INT_ENA_W<'_, 4>

Bit 4 - The interrupt enable bit for CH0_ERR_INT.

pub fn ch1_tx_err_int_ena(&mut self) -> CH_TX_ERR_INT_ENA_W<'_, 5>

Bit 5 - The interrupt enable bit for CH1_ERR_INT.

pub fn ch2_tx_err_int_ena(&mut self) -> CH_TX_ERR_INT_ENA_W<'_, 6>

Bit 6 - The interrupt enable bit for CH2_ERR_INT.

pub fn ch3_tx_err_int_ena(&mut self) -> CH_TX_ERR_INT_ENA_W<'_, 7>

Bit 7 - The interrupt enable bit for CH3_ERR_INT.

pub unsafe fn ch_tx_thr_event_int_ena<const O: u8>(
    &mut self
) -> CH_TX_THR_EVENT_INT_ENA_W<'_, O>

The interrupt enable bit for CH[0-3]_TX_THR_EVENT_INT.

pub fn ch0_tx_thr_event_int_ena(&mut self) -> CH_TX_THR_EVENT_INT_ENA_W<'_, 8>

Bit 8 - The interrupt enable bit for CH0_TX_THR_EVENT_INT.

pub fn ch1_tx_thr_event_int_ena(&mut self) -> CH_TX_THR_EVENT_INT_ENA_W<'_, 9>

Bit 9 - The interrupt enable bit for CH1_TX_THR_EVENT_INT.

pub fn ch2_tx_thr_event_int_ena(&mut self) -> CH_TX_THR_EVENT_INT_ENA_W<'_, 10>

Bit 10 - The interrupt enable bit for CH2_TX_THR_EVENT_INT.

pub fn ch3_tx_thr_event_int_ena(&mut self) -> CH_TX_THR_EVENT_INT_ENA_W<'_, 11>

Bit 11 - The interrupt enable bit for CH3_TX_THR_EVENT_INT.

pub unsafe fn ch_tx_loop_int_ena<const O: u8>(
    &mut self
) -> CH_TX_LOOP_INT_ENA_W<'_, O>

The interrupt enable bit for CH[0-3]_TX_LOOP_INT.

pub fn ch0_tx_loop_int_ena(&mut self) -> CH_TX_LOOP_INT_ENA_W<'_, 12>

Bit 12 - The interrupt enable bit for CH0_TX_LOOP_INT.

pub fn ch1_tx_loop_int_ena(&mut self) -> CH_TX_LOOP_INT_ENA_W<'_, 13>

Bit 13 - The interrupt enable bit for CH1_TX_LOOP_INT.

pub fn ch2_tx_loop_int_ena(&mut self) -> CH_TX_LOOP_INT_ENA_W<'_, 14>

Bit 14 - The interrupt enable bit for CH2_TX_LOOP_INT.

pub fn ch3_tx_loop_int_ena(&mut self) -> CH_TX_LOOP_INT_ENA_W<'_, 15>

Bit 15 - The interrupt enable bit for CH3_TX_LOOP_INT.

pub unsafe fn ch_rx_end_int_ena<const O: u8>(
    &mut self
) -> CH_RX_END_INT_ENA_W<'_, O>

The interrupt enable bit for CH4_RX_END_INT.

pub fn ch4_rx_end_int_ena(&mut self) -> CH_RX_END_INT_ENA_W<'_, 16>

Bit 16 - The interrupt enable bit for CH4_RX_END_INT.

pub fn ch5_rx_end_int_ena(&mut self) -> CH_RX_END_INT_ENA_W<'_, 17>

Bit 17 - The interrupt enable bit for CH4_RX_END_INT.

pub fn ch6_rx_end_int_ena(&mut self) -> CH_RX_END_INT_ENA_W<'_, 18>

Bit 18 - The interrupt enable bit for CH4_RX_END_INT.

pub fn ch7_rx_end_int_ena(&mut self) -> CH_RX_END_INT_ENA_W<'_, 19>

Bit 19 - The interrupt enable bit for CH4_RX_END_INT.

pub unsafe fn ch_rx_err_int_ena<const O: u8>(
    &mut self
) -> CH_RX_ERR_INT_ENA_W<'_, O>

The interrupt enable bit for CH4_ERR_INT.

pub fn ch4_rx_err_int_ena(&mut self) -> CH_RX_ERR_INT_ENA_W<'_, 20>

Bit 20 - The interrupt enable bit for CH4_ERR_INT.

pub fn ch5_rx_err_int_ena(&mut self) -> CH_RX_ERR_INT_ENA_W<'_, 21>

Bit 21 - The interrupt enable bit for CH4_ERR_INT.

pub fn ch6_rx_err_int_ena(&mut self) -> CH_RX_ERR_INT_ENA_W<'_, 22>

Bit 22 - The interrupt enable bit for CH4_ERR_INT.

pub fn ch7_rx_err_int_ena(&mut self) -> CH_RX_ERR_INT_ENA_W<'_, 23>

Bit 23 - The interrupt enable bit for CH4_ERR_INT.

pub fn ch4_rx_thr_event_int_ena(&mut self) -> CH4_RX_THR_EVENT_INT_ENA_W<'_, 24>

Bit 24 - The interrupt enable bit for CH4_RX_THR_EVENT_INT.

pub fn ch5_rx_thr_event_int_ena(&mut self) -> CH5_RX_THR_EVENT_INT_ENA_W<'_, 25>

Bit 25 - The interrupt enable bit for CH5_RX_THR_EVENT_INT.

pub fn ch6_rx_thr_event_int_ena(&mut self) -> CH6_RX_THR_EVENT_INT_ENA_W<'_, 26>

Bit 26 - The interrupt enable bit for CH6_RX_THR_EVENT_INT.

pub fn ch7_rx_thr_event_int_ena(&mut self) -> CH7_RX_THR_EVENT_INT_ENA_W<'_, 27>

Bit 27 - The interrupt enable bit for CH7_RX_THR_EVENT_INT.

pub fn tx_ch3_dma_access_fail_int_ena(
    &mut self
) -> TX_CH3_DMA_ACCESS_FAIL_INT_ENA_W<'_, 28>

Bit 28 - The interrupt enable bit for CH3_DMA_ACCESS_FAIL_INT.

pub fn rx_ch7_dma_access_fail_int_ena(
    &mut self
) -> RX_CH7_DMA_ACCESS_FAIL_INT_ENA_W<'_, 29>

Bit 29 - The interrupt enable bit for CH7_DMA_ACCESS_FAIL_INT.

pub unsafe fn bits(&mut self, bits: u32) -> &mut Self

Writes raw bits to the register.

Methods from Deref<Target = W<INT_ENA_SPEC>>

pub unsafe fn bits(&mut self, bits: REG::Ux) -> &mut Self

Writes raw bits to the register.

Safety

Read datasheet or reference manual to find what values are allowed to pass.

Trait Implementations

impl Deref for W

type Target = W<INT_ENA_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &Self::Target

Dereferences the value.

impl DerefMut for W

fn deref_mut(&mut self) -> &mut Self::Target

Mutably dereferences the value.

impl From<W<INT_ENA_SPEC>> for W

fn from(writer: W<INT_ENA_SPEC>) -> Self

Converts to this type from the input type.