Struct esp32s3::debug_assist::core_0_interrupt_ena::W
source · pub struct W(_);
Expand description
Register CORE_0_INTERRUPT_ENA
writer
Implementations§
source§impl W
impl W
sourcepub fn core_0_area_dram0_0_rd_ena(
&mut self
) -> CORE_0_AREA_DRAM0_0_RD_ENA_W<'_, 0>
pub fn core_0_area_dram0_0_rd_ena(
&mut self
) -> CORE_0_AREA_DRAM0_0_RD_ENA_W<'_, 0>
Bit 0 - Core0 dram0 area0 read monitor enable
sourcepub fn core_0_area_dram0_0_wr_ena(
&mut self
) -> CORE_0_AREA_DRAM0_0_WR_ENA_W<'_, 1>
pub fn core_0_area_dram0_0_wr_ena(
&mut self
) -> CORE_0_AREA_DRAM0_0_WR_ENA_W<'_, 1>
Bit 1 - Core0 dram0 area0 write monitor enable
sourcepub fn core_0_area_dram0_1_rd_ena(
&mut self
) -> CORE_0_AREA_DRAM0_1_RD_ENA_W<'_, 2>
pub fn core_0_area_dram0_1_rd_ena(
&mut self
) -> CORE_0_AREA_DRAM0_1_RD_ENA_W<'_, 2>
Bit 2 - Core0 dram0 area1 read monitor enable
sourcepub fn core_0_area_dram0_1_wr_ena(
&mut self
) -> CORE_0_AREA_DRAM0_1_WR_ENA_W<'_, 3>
pub fn core_0_area_dram0_1_wr_ena(
&mut self
) -> CORE_0_AREA_DRAM0_1_WR_ENA_W<'_, 3>
Bit 3 - Core0 dram0 area1 write monitor enable
sourcepub fn core_0_area_pif_0_rd_ena(&mut self) -> CORE_0_AREA_PIF_0_RD_ENA_W<'_, 4>
pub fn core_0_area_pif_0_rd_ena(&mut self) -> CORE_0_AREA_PIF_0_RD_ENA_W<'_, 4>
Bit 4 - Core0 PIF area0 read monitor enable
sourcepub fn core_0_area_pif_0_wr_ena(&mut self) -> CORE_0_AREA_PIF_0_WR_ENA_W<'_, 5>
pub fn core_0_area_pif_0_wr_ena(&mut self) -> CORE_0_AREA_PIF_0_WR_ENA_W<'_, 5>
Bit 5 - Core0 PIF area0 write monitor enable
sourcepub fn core_0_area_pif_1_rd_ena(&mut self) -> CORE_0_AREA_PIF_1_RD_ENA_W<'_, 6>
pub fn core_0_area_pif_1_rd_ena(&mut self) -> CORE_0_AREA_PIF_1_RD_ENA_W<'_, 6>
Bit 6 - Core0 PIF area1 read monitor enable
sourcepub fn core_0_area_pif_1_wr_ena(&mut self) -> CORE_0_AREA_PIF_1_WR_ENA_W<'_, 7>
pub fn core_0_area_pif_1_wr_ena(&mut self) -> CORE_0_AREA_PIF_1_WR_ENA_W<'_, 7>
Bit 7 - Core0 PIF area1 write monitor enable
sourcepub fn core_0_sp_spill_min_ena(&mut self) -> CORE_0_SP_SPILL_MIN_ENA_W<'_, 8>
pub fn core_0_sp_spill_min_ena(&mut self) -> CORE_0_SP_SPILL_MIN_ENA_W<'_, 8>
Bit 8 - Core0 stackpoint overflow monitor enable
sourcepub fn core_0_sp_spill_max_ena(&mut self) -> CORE_0_SP_SPILL_MAX_ENA_W<'_, 9>
pub fn core_0_sp_spill_max_ena(&mut self) -> CORE_0_SP_SPILL_MAX_ENA_W<'_, 9>
Bit 9 - Core0 stackpoint underflow monitor enable
sourcepub fn core_0_iram0_exception_monitor_ena(
&mut self
) -> CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_W<'_, 10>
pub fn core_0_iram0_exception_monitor_ena(
&mut self
) -> CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_W<'_, 10>
Bit 10 - IBUS busy monitor enable
sourcepub fn core_0_dram0_exception_monitor_ena(
&mut self
) -> CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_W<'_, 11>
pub fn core_0_dram0_exception_monitor_ena(
&mut self
) -> CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_W<'_, 11>
Bit 11 - DBUS busy monitor enbale