Struct esp32s3::sensitive::core_0_pif_pms_constrain_8::W

pub struct W(_);

Register CORE_0_PIF_PMS_CONSTRAIN_8 writer

Implementations

impl W

pub fn core_0_pif_pms_constrain_world_1_usb_device(
    &mut self
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE_W<'_, 0>

Bits 0:1 - Core0 access usb_device permission in world1.

pub fn core_0_pif_pms_constrain_world_1_usb_wrap(
    &mut self
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP_W<'_, 2>

Bits 2:3 - Core0 access usb_wrap permission in world1.

pub fn core_0_pif_pms_constrain_world_1_crypto_peri(
    &mut self
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_W<'_, 4>

Bits 4:5 - Core0 access crypto_peri permission in world1.

pub fn core_0_pif_pms_constrain_world_1_crypto_dma(
    &mut self
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_W<'_, 6>

Bits 6:7 - Core0 access crypto_dma permission in world1.

pub fn core_0_pif_pms_constrain_world_1_apb_adc(
    &mut self
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_W<'_, 8>

Bits 8:9 - Core0 access apb_adc permission in world1.

pub fn core_0_pif_pms_constrain_world_1_lcd_cam(
    &mut self
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM_W<'_, 10>

Bits 10:11 - Core0 access lcd_cam permission in world1.

pub fn core_0_pif_pms_constrain_world_1_bt_pwr(
    &mut self
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR_W<'_, 12>

Bits 12:13 - Core0 access bt_pwr permission in world1.

pub fn core_0_pif_pms_constrain_world_1_usb(
    &mut self
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_W<'_, 14>

Bits 14:15 - Core0 access usb permission in world1.

pub fn core_0_pif_pms_constrain_world_1_system(
    &mut self
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_W<'_, 16>

Bits 16:17 - Core0 access system permission in world1.

pub fn core_0_pif_pms_constrain_world_1_sensitive(
    &mut self
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_W<'_, 18>

Bits 18:19 - Core0 access sensitive permission in world1.

pub fn core_0_pif_pms_constrain_world_1_interrupt(
    &mut self
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_W<'_, 20>

Bits 20:21 - Core0 access interrupt permission in world1.

pub fn core_0_pif_pms_constrain_world_1_dma_copy(
    &mut self
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_W<'_, 22>

Bits 22:23 - Core0 access dma_copy permission in world1.

pub fn core_0_pif_pms_constrain_world_1_cache_config(
    &mut self
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_W<'_, 24>

Bits 24:25 - Core0 access cache_config permission in world1.

pub fn core_0_pif_pms_constrain_world_1_ad(
    &mut self
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD_W<'_, 26>

Bits 26:27 - Core0 access ad permission in world1.

pub fn core_0_pif_pms_constrain_world_1_dio(
    &mut self
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO_W<'_, 28>

Bits 28:29 - Core0 access dio permission in world1.

pub fn core_0_pif_pms_constrain_world_1_world_controller(
    &mut self
) -> CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_W<'_, 30>

Bits 30:31 - Core0 access world_controller permission in world1.

pub unsafe fn bits(&mut self, bits: u32) -> &mut Self

Writes raw bits to the register.

Methods from Deref<Target = W<CORE_0_PIF_PMS_CONSTRAIN_8_SPEC>>

pub unsafe fn bits(&mut self, bits: REG::Ux) -> &mut Self

Writes raw bits to the register.

Safety

Read datasheet or reference manual to find what values are allowed to pass.

Trait Implementations

impl Deref for W

type Target = W<CORE_0_PIF_PMS_CONSTRAIN_8_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &Self::Target

Dereferences the value.

impl DerefMut for W

fn deref_mut(&mut self) -> &mut Self::Target

Mutably dereferences the value.

impl From<W<CORE_0_PIF_PMS_CONSTRAIN_8_SPEC>> for W

fn from(writer: W<CORE_0_PIF_PMS_CONSTRAIN_8_SPEC>) -> Self

Converts to this type from the input type.