Struct esp32s3::debug_assist::core_1_interrupt_ena::R

pub struct R(_);

Register CORE_1_INTERRUPT_ENA reader

Implementations

impl R

pub fn core_1_area_dram0_0_rd_ena(&self) -> CORE_1_AREA_DRAM0_0_RD_ENA_R

Bit 0 - Core1 dram0 area0 read monitor enable

pub fn core_1_area_dram0_0_wr_ena(&self) -> CORE_1_AREA_DRAM0_0_WR_ENA_R

Bit 1 - Core1 dram0 area0 write monitor enable

pub fn core_1_area_dram0_1_rd_ena(&self) -> CORE_1_AREA_DRAM0_1_RD_ENA_R

Bit 2 - Core1 dram0 area1 read monitor enable

pub fn core_1_area_dram0_1_wr_ena(&self) -> CORE_1_AREA_DRAM0_1_WR_ENA_R

Bit 3 - Core1 dram0 area1 write monitor enable

pub fn core_1_area_pif_0_rd_ena(&self) -> CORE_1_AREA_PIF_0_RD_ENA_R

Bit 4 - Core1 PIF area0 read monitor enable

pub fn core_1_area_pif_0_wr_ena(&self) -> CORE_1_AREA_PIF_0_WR_ENA_R

Bit 5 - Core1 PIF area0 write monitor enable

pub fn core_1_area_pif_1_rd_ena(&self) -> CORE_1_AREA_PIF_1_RD_ENA_R

Bit 6 - Core1 PIF area1 read monitor enable

pub fn core_1_area_pif_1_wr_ena(&self) -> CORE_1_AREA_PIF_1_WR_ENA_R

Bit 7 - Core1 PIF area1 write monitor enable

pub fn core_1_sp_spill_min_ena(&self) -> CORE_1_SP_SPILL_MIN_ENA_R

Bit 8 - Core1 stackpoint overflow monitor enable

pub fn core_1_sp_spill_max_ena(&self) -> CORE_1_SP_SPILL_MAX_ENA_R

Bit 9 - Core1 stackpoint underflow monitor enable

pub fn core_1_iram0_exception_monitor_ena(
    &self
) -> CORE_1_IRAM0_EXCEPTION_MONITOR_ENA_R

Bit 10 - IBUS busy monitor enable

pub fn core_1_dram0_exception_monitor_ena(
    &self
) -> CORE_1_DRAM0_EXCEPTION_MONITOR_ENA_R

Bit 11 - DBUS busy monitor enbale

Methods from Deref<Target = R<CORE_1_INTERRUPT_ENA_SPEC>>

pub fn bits(&self) -> REG::Ux

Reads raw bits from register.

Trait Implementations

impl Deref for R

type Target = R<CORE_1_INTERRUPT_ENA_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &Self::Target

Dereferences the value.

impl From<R<CORE_1_INTERRUPT_ENA_SPEC>> for R

fn from(reader: R<CORE_1_INTERRUPT_ENA_SPEC>) -> Self

Converts to this type from the input type.