pub struct W(_);
Expand description
Register CAM_CTRL
writer
Implementations§
source§impl W
impl W
sourcepub fn cam_stop_en(&mut self) -> CAM_STOP_EN_W<'_, 0>
pub fn cam_stop_en(&mut self) -> CAM_STOP_EN_W<'_, 0>
Bit 0 - Camera stop enable signal, 1: camera stops when DMA Rx FIFO is full. 0: Not stop.
sourcepub fn cam_vsync_filter_thres(&mut self) -> CAM_VSYNC_FILTER_THRES_W<'_, 1>
pub fn cam_vsync_filter_thres(&mut self) -> CAM_VSYNC_FILTER_THRES_W<'_, 1>
Bits 1:3 - Filter threshold value for CAM_VSYNC signal.
sourcepub fn cam_update(&mut self) -> CAM_UPDATE_W<'_, 4>
pub fn cam_update(&mut self) -> CAM_UPDATE_W<'_, 4>
Bit 4 - 1: Update Camera registers, will be cleared by hardware. 0 : Not care.
sourcepub fn cam_byte_order(&mut self) -> CAM_BYTE_ORDER_W<'_, 5>
pub fn cam_byte_order(&mut self) -> CAM_BYTE_ORDER_W<'_, 5>
Bit 5 - 1: Change data bit order, change CAM_DATA_in[7:0] to CAM_DATA_in[0:7] in one byte mode, and bits[15:0] to bits[0:15] in two byte mode. 0: Not change.
sourcepub fn cam_bit_order(&mut self) -> CAM_BIT_ORDER_W<'_, 6>
pub fn cam_bit_order(&mut self) -> CAM_BIT_ORDER_W<'_, 6>
Bit 6 - 1: invert data byte order, only valid in 2 byte mode. 0: Not change.
sourcepub fn cam_line_int_en(&mut self) -> CAM_LINE_INT_EN_W<'_, 7>
pub fn cam_line_int_en(&mut self) -> CAM_LINE_INT_EN_W<'_, 7>
Bit 7 - 1: Enable to generate CAM_HS_INT. 0: Disable.
sourcepub fn cam_vs_eof_en(&mut self) -> CAM_VS_EOF_EN_W<'_, 8>
pub fn cam_vs_eof_en(&mut self) -> CAM_VS_EOF_EN_W<'_, 8>
Bit 8 - 1: CAM_VSYNC to generate in_suc_eof. 0: in_suc_eof is controlled by reg_cam_rec_data_cyclelen.
sourcepub fn cam_clkm_div_num(&mut self) -> CAM_CLKM_DIV_NUM_W<'_, 9>
pub fn cam_clkm_div_num(&mut self) -> CAM_CLKM_DIV_NUM_W<'_, 9>
Bits 9:16 - Integral Camera clock divider value
sourcepub fn cam_clkm_div_b(&mut self) -> CAM_CLKM_DIV_B_W<'_, 17>
pub fn cam_clkm_div_b(&mut self) -> CAM_CLKM_DIV_B_W<'_, 17>
Bits 17:22 - Fractional clock divider numerator value
sourcepub fn cam_clkm_div_a(&mut self) -> CAM_CLKM_DIV_A_W<'_, 23>
pub fn cam_clkm_div_a(&mut self) -> CAM_CLKM_DIV_A_W<'_, 23>
Bits 23:28 - Fractional clock divider denominator value
sourcepub fn cam_clk_sel(&mut self) -> CAM_CLK_SEL_W<'_, 29>
pub fn cam_clk_sel(&mut self) -> CAM_CLK_SEL_W<'_, 29>
Bits 29:30 - Select Camera module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: no clock.