Struct esp32s3_hal::peripherals::SPI1
source · pub struct SPI1 { /* private fields */ }
Implementations§
source§impl SPI1
impl SPI1
sourcepub unsafe fn steal() -> SPI1
pub unsafe fn steal() -> SPI1
Unsafely create an instance of this peripheral out of thin air.
§Safety
You must ensure that you’re only using one instance of this type at a time.
Methods from Deref<Target = RegisterBlock>§
sourcepub fn ctrl1(&self) -> &Reg<CTRL1_SPEC>
pub fn ctrl1(&self) -> &Reg<CTRL1_SPEC>
0x0c - SPI1 control1 register
sourcepub fn ctrl2(&self) -> &Reg<CTRL2_SPEC>
pub fn ctrl2(&self) -> &Reg<CTRL2_SPEC>
0x10 - SPI1 control2 register
sourcepub fn clock(&self) -> &Reg<CLOCK_SPEC>
pub fn clock(&self) -> &Reg<CLOCK_SPEC>
0x14 - SPI_CLK clock division register when SPI1 accesses to flash or Ext_RAM.
sourcepub fn user1(&self) -> &Reg<USER1_SPEC>
pub fn user1(&self) -> &Reg<USER1_SPEC>
0x1c - SPI1 user1 register.
sourcepub fn user2(&self) -> &Reg<USER2_SPEC>
pub fn user2(&self) -> &Reg<USER2_SPEC>
0x20 - SPI1 user2 register.
sourcepub fn mosi_dlen(&self) -> &Reg<MOSI_DLEN_SPEC>
pub fn mosi_dlen(&self) -> &Reg<MOSI_DLEN_SPEC>
0x24 - SPI1 write-data bit length register.
sourcepub fn miso_dlen(&self) -> &Reg<MISO_DLEN_SPEC>
pub fn miso_dlen(&self) -> &Reg<MISO_DLEN_SPEC>
0x28 - SPI1 read-data bit length register.
sourcepub fn rd_status(&self) -> &Reg<RD_STATUS_SPEC>
pub fn rd_status(&self) -> &Reg<RD_STATUS_SPEC>
0x2c - SPI1 read control register.
sourcepub fn ext_addr(&self) -> &Reg<EXT_ADDR_SPEC>
pub fn ext_addr(&self) -> &Reg<EXT_ADDR_SPEC>
0x30 - SPI1 extended address register.
sourcepub fn tx_crc(&self) -> &Reg<TX_CRC_SPEC>
pub fn tx_crc(&self) -> &Reg<TX_CRC_SPEC>
0x38 - SPI1 CRC data register.
sourcepub fn cache_fctrl(&self) -> &Reg<CACHE_FCTRL_SPEC>
pub fn cache_fctrl(&self) -> &Reg<CACHE_FCTRL_SPEC>
0x3c - SPI1 bit mode control register.
sourcepub fn flash_waiti_ctrl(&self) -> &Reg<FLASH_WAITI_CTRL_SPEC>
pub fn flash_waiti_ctrl(&self) -> &Reg<FLASH_WAITI_CTRL_SPEC>
0x98 - SPI1 wait idle control register
sourcepub fn flash_sus_cmd(&self) -> &Reg<FLASH_SUS_CMD_SPEC>
pub fn flash_sus_cmd(&self) -> &Reg<FLASH_SUS_CMD_SPEC>
0x9c - SPI1 flash suspend control register
sourcepub fn flash_sus_ctrl(&self) -> &Reg<FLASH_SUS_CTRL_SPEC>
pub fn flash_sus_ctrl(&self) -> &Reg<FLASH_SUS_CTRL_SPEC>
0xa0 - SPI1 flash suspend command register
sourcepub fn sus_status(&self) -> &Reg<SUS_STATUS_SPEC>
pub fn sus_status(&self) -> &Reg<SUS_STATUS_SPEC>
0xa4 - SPI1 flash suspend status register
sourcepub fn timing_cali(&self) -> &Reg<TIMING_CALI_SPEC>
pub fn timing_cali(&self) -> &Reg<TIMING_CALI_SPEC>
0xa8 - SPI1 timing compensation register when accesses to flash or Ext_RAM.
sourcepub fn clock_gate(&self) -> &Reg<CLOCK_GATE_SPEC>
pub fn clock_gate(&self) -> &Reg<CLOCK_GATE_SPEC>
0xe8 - SPI1 clk_gate register
sourcepub fn int_ena(&self) -> &Reg<INT_ENA_SPEC>
pub fn int_ena(&self) -> &Reg<INT_ENA_SPEC>
0xf0 - SPI1 interrupt enable register
sourcepub fn int_clr(&self) -> &Reg<INT_CLR_SPEC>
pub fn int_clr(&self) -> &Reg<INT_CLR_SPEC>
0xf4 - SPI1 interrupt clear register
sourcepub fn int_raw(&self) -> &Reg<INT_RAW_SPEC>
pub fn int_raw(&self) -> &Reg<INT_RAW_SPEC>
0xf8 - SPI1 interrupt raw register
sourcepub fn int_st(&self) -> &Reg<INT_ST_SPEC>
pub fn int_st(&self) -> &Reg<INT_ST_SPEC>
0xfc - SPI1 interrupt status register