Struct esp32s3_hal::peripherals::SPI0

pub struct SPI0 { /* private fields */ }

Implementations

impl SPI0

pub unsafe fn steal() -> SPI0

Unsafely create an instance of this peripheral out of thin air.

Safety

You must ensure that you’re only using one instance of this type at a time.

pub const PTR: *const <SPI0 as Deref>::Target = {0x60003000 as *const <esp32s3::SPI0 as core::ops::Deref>::Target}

Pointer to the register block

pub const fn ptr() -> *const <SPI0 as Deref>::Target

Return the pointer to the register block

Methods from Deref<Target = RegisterBlock>

pub fn ctrl(&self) -> &Reg<CTRL_SPEC>

0x08 - SPI0 control register.

pub fn ctrl1(&self) -> &Reg<CTRL1_SPEC>

0x0c - SPI0 control 1 register.

pub fn ctrl2(&self) -> &Reg<CTRL2_SPEC>

0x10 - SPI0 control 2 register.

pub fn clock(&self) -> &Reg<CLOCK_SPEC>

0x14 - SPI_CLK clock division register when SPI0 accesses to flash.

pub fn user(&self) -> &Reg<USER_SPEC>

0x18 - SPI0 user register.

pub fn user1(&self) -> &Reg<USER1_SPEC>

0x1c - SPI0 user1 register.

pub fn user2(&self) -> &Reg<USER2_SPEC>

0x20 - SPI0 user2 register.

pub fn rd_status(&self) -> &Reg<RD_STATUS_SPEC>

0x2c - SPI0 read control register.

pub fn ext_addr(&self) -> &Reg<EXT_ADDR_SPEC>

0x30 - SPI0 extended address register.

pub fn misc(&self) -> &Reg<MISC_SPEC>

0x34 - SPI0 misc register

pub fn cache_fctrl(&self) -> &Reg<CACHE_FCTRL_SPEC>

0x3c - SPI0 external RAM bit mode control register.

pub fn cache_sctrl(&self) -> &Reg<CACHE_SCTRL_SPEC>

0x40 - SPI0 external RAM control register

pub fn sram_cmd(&self) -> &Reg<SRAM_CMD_SPEC>

0x44 - SPI0 external RAM mode control register

pub fn sram_drd_cmd(&self) -> &Reg<SRAM_DRD_CMD_SPEC>

0x48 - SPI0 external RAM DDR read command control register

pub fn sram_dwr_cmd(&self) -> &Reg<SRAM_DWR_CMD_SPEC>

0x4c - SPI0 external RAM DDR write command control register

pub fn sram_clk(&self) -> &Reg<SRAM_CLK_SPEC>

0x50 - SPI_CLK clock division register when SPI0 accesses to Ext_RAM.

pub fn fsm(&self) -> &Reg<FSM_SPEC>

0x54 - SPI0 state machine(FSM) status register.

pub fn timing_cali(&self) -> &Reg<TIMING_CALI_SPEC>

0xa8 - SPI0 timing compensation register when accesses to flash.

pub fn din_mode(&self) -> &Reg<DIN_MODE_SPEC>

0xac - MSPI input timing delay mode control register when accesses to flash.

pub fn din_num(&self) -> &Reg<DIN_NUM_SPEC>

0xb0 - MSPI input timing delay number control register when accesses to flash.

pub fn dout_mode(&self) -> &Reg<DOUT_MODE_SPEC>

0xb4 - MSPI output timing delay mode control register when accesses to flash.

pub fn spi_smem_timing_cali(&self) -> &Reg<SPI_SMEM_TIMING_CALI_SPEC>

0xbc - SPI0 Ext_RAM timing compensation register.

pub fn spi_smem_din_mode(&self) -> &Reg<SPI_SMEM_DIN_MODE_SPEC>

0xc0 - MSPI input timing delay mode control register when accesses to Ext_RAM.

pub fn spi_smem_din_num(&self) -> &Reg<SPI_SMEM_DIN_NUM_SPEC>

0xc4 - MSPI input timing delay number control register when accesses to Ext_RAM.

pub fn spi_smem_dout_mode(&self) -> &Reg<SPI_SMEM_DOUT_MODE_SPEC>

0xc8 - MSPI output timing delay mode control register when accesses to Ext_RAM.

pub fn ecc_ctrl(&self) -> &Reg<ECC_CTRL_SPEC>

0xcc - MSPI ECC control register

pub fn ecc_err_addr(&self) -> &Reg<ECC_ERR_ADDR_SPEC>

0xd0 - MSPI ECC error address register

pub fn ecc_err_bit(&self) -> &Reg<ECC_ERR_BIT_SPEC>

0xd4 - MSPI ECC error bits register

pub fn spi_smem_ac(&self) -> &Reg<SPI_SMEM_AC_SPEC>

0xdc - MSPI external RAM ECC and SPI CS timing control register

pub fn ddr(&self) -> &Reg<DDR_SPEC>

0xe0 - SPI0 flash DDR mode control register

pub fn spi_smem_ddr(&self) -> &Reg<SPI_SMEM_DDR_SPEC>

0xe4 - SPI0 external RAM DDR mode control register

pub fn clock_gate(&self) -> &Reg<CLOCK_GATE_SPEC>

0xe8 - SPI0 clk_gate register

pub fn core_clk_sel(&self) -> &Reg<CORE_CLK_SEL_SPEC>

0xec - SPI0 module clock select register

pub fn int_ena(&self) -> &Reg<INT_ENA_SPEC>

0xf0 - SPI1 interrupt enable register

pub fn int_clr(&self) -> &Reg<INT_CLR_SPEC>

0xf4 - SPI1 interrupt clear register

pub fn int_raw(&self) -> &Reg<INT_RAW_SPEC>

0xf8 - SPI1 interrupt raw register

pub fn int_st(&self) -> &Reg<INT_ST_SPEC>

0xfc - SPI1 interrupt status register

pub fn date(&self) -> &Reg<DATE_SPEC>

0x3fc - SPI0 version control register

Trait Implementations

impl Debug for SPI0

fn fmt(&self, f: &mut Formatter<'_>) -> Result<(), Error>

Formats the value using the given formatter.

impl Deref for SPI0

type Target = <SPI0 as Deref>::Target

The resulting type after dereferencing.

fn deref(&self) -> &<SPI0 as Deref>::Target

Dereferences the value.

impl DerefMut for SPI0

fn deref_mut(&mut self) -> &mut <SPI0 as Deref>::Target

Mutably dereferences the value.

impl Peripheral for SPI0

type P = SPI0

Peripheral singleton type

unsafe fn clone_unchecked(&mut self) -> <SPI0 as Peripheral>::P

Unsafely clone (duplicate) a peripheral singleton.

fn into_ref<'a>(self) -> PeripheralRef<'a, Self::P>

where Self: 'a,

Convert a value into a PeripheralRef.