Struct esp32s3_hal::peripherals::RMT

impl RMT

pub unsafe fn steal() -> RMT

Unsafely create an instance of this peripheral out of thin air.

§Safety

You must ensure that you’re only using one instance of this type at a time.

pub const PTR: const <RMT as Deref>::Target = {0x60016000 as const <esp32s3::RMT as core::ops::Deref>::Target}

Pointer to the register block

pub const fn ptr() -> *const <RMT as Deref>::Target

Return the pointer to the register block

Methods from Deref<Target = RegisterBlock>§

pub fn chdata(&self, n: usize) -> &Reg<CHDATA_SPEC>

0x00..0x20 - The read and write data register for CHANNEL%s by apb fifo access.

pub fn chdata_iter(&self) -> impl Iterator<Item = &Reg<CHDATA_SPEC>>

Iterator for array of: 0x00..0x20 - The read and write data register for CHANNEL%s by apb fifo access.

pub fn ch0data(&self) -> &Reg<CHDATA_SPEC>

0x00 - The read and write data register for CHANNEL0 by apb fifo access.

pub fn ch1data(&self) -> &Reg<CHDATA_SPEC>

0x04 - The read and write data register for CHANNEL1 by apb fifo access.

pub fn ch2data(&self) -> &Reg<CHDATA_SPEC>

0x08 - The read and write data register for CHANNEL2 by apb fifo access.

pub fn ch3data(&self) -> &Reg<CHDATA_SPEC>

0x0c - The read and write data register for CHANNEL3 by apb fifo access.

pub fn ch4data(&self) -> &Reg<CHDATA_SPEC>

0x10 - The read and write data register for CHANNEL4 by apb fifo access.

pub fn ch5data(&self) -> &Reg<CHDATA_SPEC>

0x14 - The read and write data register for CHANNEL5 by apb fifo access.

pub fn ch6data(&self) -> &Reg<CHDATA_SPEC>

0x18 - The read and write data register for CHANNEL6 by apb fifo access.

pub fn ch7data(&self) -> &Reg<CHDATA_SPEC>

0x1c - The read and write data register for CHANNEL7 by apb fifo access.

pub fn ch_tx_conf0(&self, n: usize) -> &Reg<CH_TX_CONF0_SPEC>

0x20..0x30 - Channel %s configure register 0

pub fn ch_tx_conf0_iter(&self) -> impl Iterator<Item = &Reg<CH_TX_CONF0_SPEC>>

Iterator for array of: 0x20..0x30 - Channel %s configure register 0

pub fn ch0_tx_conf0(&self) -> &Reg<CH_TX_CONF0_SPEC>

0x20 - Channel 0 configure register 0

pub fn ch1_tx_conf0(&self) -> &Reg<CH_TX_CONF0_SPEC>

0x24 - Channel 1 configure register 0

pub fn ch2_tx_conf0(&self) -> &Reg<CH_TX_CONF0_SPEC>

0x28 - Channel 2 configure register 0

pub fn ch3_tx_conf0(&self) -> &Reg<CH_TX_CONF0_SPEC>

0x2c - Channel 3 configure register 0

pub fn ch_rx_conf0(&self, n: usize) -> &Reg<CH_RX_CONF0_SPEC>

0x30..0x40 - Channel %s configure register 0

pub fn ch_rx_conf0_iter(&self) -> impl Iterator<Item = &Reg<CH_RX_CONF0_SPEC>>

Iterator for array of: 0x30..0x40 - Channel %s configure register 0

pub fn ch4_rx_conf0(&self) -> &Reg<CH_RX_CONF0_SPEC>

0x30 - Channel 4 configure register 0

pub fn ch5_rx_conf0(&self) -> &Reg<CH_RX_CONF0_SPEC>

0x38 - Channel 5 configure register 0

pub fn ch6_rx_conf0(&self) -> &Reg<CH_RX_CONF0_SPEC>

0x40 - Channel 6 configure register 0

pub fn ch7_rx_conf0(&self) -> &Reg<CH_RX_CONF0_SPEC>

0x48 - Channel 7 configure register 0

pub fn ch_rx_conf1(&self, n: usize) -> &Reg<CH_RX_CONF1_SPEC>

0x34..0x44 - Channel %s configure register 1

pub fn ch_rx_conf1_iter(&self) -> impl Iterator<Item = &Reg<CH_RX_CONF1_SPEC>>

Iterator for array of: 0x34..0x44 - Channel %s configure register 1

pub fn ch4_rx_conf1(&self) -> &Reg<CH_RX_CONF1_SPEC>

0x34 - Channel 4 configure register 1

pub fn ch5_rx_conf1(&self) -> &Reg<CH_RX_CONF1_SPEC>

0x3c - Channel 5 configure register 1

pub fn ch6_rx_conf1(&self) -> &Reg<CH_RX_CONF1_SPEC>

0x44 - Channel 6 configure register 1

pub fn ch7_rx_conf1(&self) -> &Reg<CH_RX_CONF1_SPEC>

0x4c - Channel 7 configure register 1

pub fn ch_tx_status(&self, n: usize) -> &Reg<CH_TX_STATUS_SPEC>

0x50..0x60 - Channel %s status register

pub fn ch_tx_status_iter(&self) -> impl Iterator<Item = &Reg<CH_TX_STATUS_SPEC>>

Iterator for array of: 0x50..0x60 - Channel %s status register

pub fn ch0_tx_status(&self) -> &Reg<CH_TX_STATUS_SPEC>

0x50 - Channel 0 status register

pub fn ch1_tx_status(&self) -> &Reg<CH_TX_STATUS_SPEC>

0x54 - Channel 1 status register

pub fn ch2_tx_status(&self) -> &Reg<CH_TX_STATUS_SPEC>

0x58 - Channel 2 status register

pub fn ch3_tx_status(&self) -> &Reg<CH_TX_STATUS_SPEC>

0x5c - Channel 3 status register

pub fn ch_rx_status(&self, n: usize) -> &Reg<CH_RX_STATUS_SPEC>

0x60..0x70 - Channel %s status register

pub fn ch_rx_status_iter(&self) -> impl Iterator<Item = &Reg<CH_RX_STATUS_SPEC>>

Iterator for array of: 0x60..0x70 - Channel %s status register

pub fn ch0_rx_status(&self) -> &Reg<CH_RX_STATUS_SPEC>

0x60 - Channel 0 status register

pub fn ch1_rx_status(&self) -> &Reg<CH_RX_STATUS_SPEC>

0x64 - Channel 1 status register

pub fn ch2_rx_status(&self) -> &Reg<CH_RX_STATUS_SPEC>

0x68 - Channel 2 status register

pub fn ch3_rx_status(&self) -> &Reg<CH_RX_STATUS_SPEC>

0x6c - Channel 3 status register

pub fn int_raw(&self) -> &Reg<INT_RAW_SPEC>

0x70 - Raw interrupt status

pub fn int_st(&self) -> &Reg<INT_ST_SPEC>

0x74 - Masked interrupt status

pub fn int_ena(&self) -> &Reg<INT_ENA_SPEC>

0x78 - Interrupt enable bits

pub fn int_clr(&self) -> &Reg<INT_CLR_SPEC>

0x7c - Interrupt clear bits

pub fn chcarrier_duty(&self, n: usize) -> &Reg<CHCARRIER_DUTY_SPEC>

0x80..0x90 - Channel %s duty cycle configuration register

pub fn chcarrier_duty_iter( &self ) -> impl Iterator<Item = &Reg<CHCARRIER_DUTY_SPEC>>

Iterator for array of: 0x80..0x90 - Channel %s duty cycle configuration register

pub fn ch0carrier_duty(&self) -> &Reg<CHCARRIER_DUTY_SPEC>

0x80 - Channel 0 duty cycle configuration register

pub fn ch1carrier_duty(&self) -> &Reg<CHCARRIER_DUTY_SPEC>

0x84 - Channel 1 duty cycle configuration register

pub fn ch2carrier_duty(&self) -> &Reg<CHCARRIER_DUTY_SPEC>

0x88 - Channel 2 duty cycle configuration register

pub fn ch3carrier_duty(&self) -> &Reg<CHCARRIER_DUTY_SPEC>

0x8c - Channel 3 duty cycle configuration register

pub fn ch_rx_carrier_rm(&self, n: usize) -> &Reg<CH_RX_CARRIER_RM_SPEC>

0x90..0xa0 - Channel %s carrier remove register

pub fn ch_rx_carrier_rm_iter( &self ) -> impl Iterator<Item = &Reg<CH_RX_CARRIER_RM_SPEC>>

Iterator for array of: 0x90..0xa0 - Channel %s carrier remove register

pub fn ch0_rx_carrier_rm(&self) -> &Reg<CH_RX_CARRIER_RM_SPEC>

0x90 - Channel 0 carrier remove register

pub fn ch1_rx_carrier_rm(&self) -> &Reg<CH_RX_CARRIER_RM_SPEC>

0x94 - Channel 1 carrier remove register

pub fn ch2_rx_carrier_rm(&self) -> &Reg<CH_RX_CARRIER_RM_SPEC>

0x98 - Channel 2 carrier remove register

pub fn ch3_rx_carrier_rm(&self) -> &Reg<CH_RX_CARRIER_RM_SPEC>

0x9c - Channel 3 carrier remove register

pub fn ch_tx_lim(&self, n: usize) -> &Reg<CH_TX_LIM_SPEC>

0xa0..0xb0 - Channel %s Tx event configuration register

pub fn ch_tx_lim_iter(&self) -> impl Iterator<Item = &Reg<CH_TX_LIM_SPEC>>

Iterator for array of: 0xa0..0xb0 - Channel %s Tx event configuration register

pub fn ch0_tx_lim(&self) -> &Reg<CH_TX_LIM_SPEC>

0xa0 - Channel 0 Tx event configuration register

pub fn ch1_tx_lim(&self) -> &Reg<CH_TX_LIM_SPEC>

0xa4 - Channel 1 Tx event configuration register

pub fn ch2_tx_lim(&self) -> &Reg<CH_TX_LIM_SPEC>

0xa8 - Channel 2 Tx event configuration register

pub fn ch3_tx_lim(&self) -> &Reg<CH_TX_LIM_SPEC>

0xac - Channel 3 Tx event configuration register

pub fn ch_rx_lim(&self, n: usize) -> &Reg<CH_RX_LIM_SPEC>

0xb0..0xc0 - Channel %s Rx event configuration register

pub fn ch_rx_lim_iter(&self) -> impl Iterator<Item = &Reg<CH_RX_LIM_SPEC>>

Iterator for array of: 0xb0..0xc0 - Channel %s Rx event configuration register

pub fn ch0_rx_lim(&self) -> &Reg<CH_RX_LIM_SPEC>

0xb0 - Channel 0 Rx event configuration register

pub fn ch1_rx_lim(&self) -> &Reg<CH_RX_LIM_SPEC>

0xb4 - Channel 1 Rx event configuration register

pub fn ch2_rx_lim(&self) -> &Reg<CH_RX_LIM_SPEC>

0xb8 - Channel 2 Rx event configuration register

pub fn ch3_rx_lim(&self) -> &Reg<CH_RX_LIM_SPEC>

0xbc - Channel 3 Rx event configuration register

pub fn sys_conf(&self) -> &Reg<SYS_CONF_SPEC>

0xc0 - RMT apb configuration register

pub fn tx_sim(&self) -> &Reg<TX_SIM_SPEC>

0xc4 - RMT TX synchronous register

pub fn ref_cnt_rst(&self) -> &Reg<REF_CNT_RST_SPEC>

0xc8 - RMT clock divider reset register

pub fn date(&self) -> &Reg<DATE_SPEC>

0xcc - RMT version register

Trait Implementations§

impl Debug for RMT

fn fmt(&self, f: &mut Formatter<'_>) -> Result<(), Error>

Formats the value using the given formatter. Read more

impl Deref for RMT

type Target = <RMT as Deref>::Target

The resulting type after dereferencing.

fn deref(&self) -> &<RMT as Deref>::Target

Dereferences the value.

impl DerefMut for RMT

fn deref_mut(&mut self) -> &mut <RMT as Deref>::Target

Mutably dereferences the value.

impl Peripheral for RMT

type P = RMT

Peripheral singleton type

unsafe fn clone_unchecked(&mut self) -> <RMT as Peripheral>::P

Unsafely clone (duplicate) a peripheral singleton. Read more

fn into_ref<'a>(self) -> PeripheralRef<'a, Self::P>
where Self: 'a,

Convert a value into a PeripheralRef. Read more

Auto Trait Implementations§

impl UnwindSafe for RMT

Blanket Implementations§

impl<T> Any for T
where T: 'static + ?Sized,

fn type_id(&self) -> TypeId

Gets the TypeId of self. Read more

impl<T> Borrow<T> for T
where T: ?Sized,

fn borrow(&self) -> &T

Immutably borrows from an owned value. Read more

impl<T> BorrowMut<T> for T
where T: ?Sized,

fn borrow_mut(&mut self) -> &mut T

Mutably borrows from an owned value. Read more

impl<T> From<T> for T

fn from(t: T) -> T

Returns the argument unchanged.

impl<T, U> Into for T
where U: From<T>,

fn into(self) -> U

Calls U::from(self).

That is, this conversion is whatever the implementation of From<T> for U chooses to do.

impl<T, U> TryFrom for T
where U: Into<T>,

type Error = Infallible

The type returned in the event of a conversion error.

fn try_from(value: U) -> Result<T, <T as TryFrom>::Error>

Performs the conversion.

impl<T, U> TryInto for T
where U: TryFrom<T>,

type Error = >::Error

The type returned in the event of a conversion error.