Struct esp32s3_hal::pac::spi2::dout_mode::W

pub struct W(_);

Expand description

Register DOUT_MODE writer

Implementations§

§

impl W

pub fn dout0_mode(
&mut self
) -> BitWriterRaw<'_, u32, DOUT_MODE_SPEC, bool, BitM, 0>

Bit 0 - The output signal 0 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.

pub fn dout1_mode(
&mut self
) -> BitWriterRaw<'_, u32, DOUT_MODE_SPEC, bool, BitM, 1>

Bit 1 - The output signal 1 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.

pub fn dout2_mode(
&mut self
) -> BitWriterRaw<'_, u32, DOUT_MODE_SPEC, bool, BitM, 2>

Bit 2 - The output signal 2 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.

pub fn dout3_mode(
&mut self
) -> BitWriterRaw<'_, u32, DOUT_MODE_SPEC, bool, BitM, 3>

Bit 3 - The output signal 3 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.

pub fn dout4_mode(
&mut self
) -> BitWriterRaw<'_, u32, DOUT_MODE_SPEC, bool, BitM, 4>

Bit 4 - The output signal 4 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.

pub fn dout5_mode(
&mut self
) -> BitWriterRaw<'_, u32, DOUT_MODE_SPEC, bool, BitM, 5>

Bit 5 - The output signal 5 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.

pub fn dout6_mode(
&mut self
) -> BitWriterRaw<'_, u32, DOUT_MODE_SPEC, bool, BitM, 6>

Bit 6 - The output signal 6 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.

pub fn dout7_mode(
&mut self
) -> BitWriterRaw<'_, u32, DOUT_MODE_SPEC, bool, BitM, 7>

Bit 7 - The output signal 7 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.

pub fn d_dqs_mode(
&mut self
) -> BitWriterRaw<'_, u32, DOUT_MODE_SPEC, bool, BitM, 8>

Bit 8 - The output signal SPI_DQS is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.