Struct esp32s3_hal::pac::spi2::clk_gate::R

pub struct R(_);

Register CLK_GATE reader

Implementations

impl R

pub fn clk_en(&self) -> BitReaderRaw<bool>

Bit 0 - Set this bit to enable clk gate

pub fn mst_clk_active(&self) -> BitReaderRaw<bool>

Bit 1 - Set this bit to power on the SPI module clock.

pub fn mst_clk_sel(&self) -> BitReaderRaw<bool>

Bit 2 - This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80M. 0: XTAL CLK.

Methods from Deref<Target = R<CLK_GATE_SPEC>>

pub fn bits(&self) -> <REG as RegisterSpec>::Ux

Reads raw bits from register.

Trait Implementations

impl Deref for R

type Target = R<CLK_GATE_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &<R as Deref>::Target

Dereferences the value.

impl From<R<CLK_GATE_SPEC>> for R

fn from(reader: R<CLK_GATE_SPEC>) -> R

Converts to this type from the input type.