Struct esp32s3_hal::pac::spi1::ctrl::W

pub struct W(_);

Register CTRL writer

Implementations

impl W

pub fn fdummy_out(&mut self) -> BitWriterRaw<'_, u32, CTRL_SPEC, bool, BitM, 3>

Bit 3 - In the DUMMY phase the signal level of SPI bus is output by the SPI0 controller.

pub fn fdout_oct(&mut self) -> BitWriterRaw<'_, u32, CTRL_SPEC, bool, BitM, 4>

Bit 4 - Set this bit to enable 8-bit-mode(8-bm) in DOUT phase.

pub fn fdin_oct(&mut self) -> BitWriterRaw<'_, u32, CTRL_SPEC, bool, BitM, 5>

Bit 5 - Set this bit to enable 8-bit-mode(8-bm) in DIN phase.

pub fn faddr_oct(&mut self) -> BitWriterRaw<'_, u32, CTRL_SPEC, bool, BitM, 6>

Bit 6 - Set this bit to enable 8-bit-mode(8-bm) in ADDR phase.

pub fn fcmd_dual(&mut self) -> BitWriterRaw<'_, u32, CTRL_SPEC, bool, BitM, 7>

Bit 7 - Set this bit to enable 2-bit-mode(2-bm) in CMD phase.

pub fn fcmd_quad(&mut self) -> BitWriterRaw<'_, u32, CTRL_SPEC, bool, BitM, 8>

Bit 8 - Set this bit to enable 4-bit-mode(4-bm) in CMD phase.

pub fn fcmd_oct(&mut self) -> BitWriterRaw<'_, u32, CTRL_SPEC, bool, BitM, 9>

Bit 9 - Set this bit to enable 8-bit-mode(8-bm) in CMD phase.

pub fn fcs_crc_en(&mut self) -> BitWriterRaw<'_, u32, CTRL_SPEC, bool, BitM, 10>

Bit 10 - For SPI1, initialize crc32 module before writing encrypted data to flash. Active low.

pub fn tx_crc_en(&mut self) -> BitWriterRaw<'_, u32, CTRL_SPEC, bool, BitM, 11>

Bit 11 - For SPI1, enable crc32 when writing encrypted data to flash. 1: enable 0:disable

pub fn fastrd_mode(
    &mut self
) -> BitWriterRaw<'_, u32, CTRL_SPEC, bool, BitM, 13>

Bit 13 - This bit should be set when SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QUAD or SPI_MEM_FREAD_DUAL is set.

pub fn fread_dual(&mut self) -> BitWriterRaw<'_, u32, CTRL_SPEC, bool, BitM, 14>

Bit 14 - In hardware 0x3B read operation, DIN phase apply 2 signals. 1: enable 0: disable.

pub fn resandres(&mut self) -> BitWriterRaw<'_, u32, CTRL_SPEC, bool, BitM, 15>

Bit 15 - The Device ID is read out to SPI_MEM_RD_STATUS register, this bit combine with spi_mem_flash_res bit. 1: enable 0: disable.

pub fn q_pol(&mut self) -> BitWriterRaw<'_, u32, CTRL_SPEC, bool, BitM, 18>

Bit 18 - The bit is used to set MISO line polarity, 1: high 0, low

pub fn d_pol(&mut self) -> BitWriterRaw<'_, u32, CTRL_SPEC, bool, BitM, 19>

Bit 19 - The bit is used to set MOSI line polarity, 1: high 0, low

pub fn fread_quad(&mut self) -> BitWriterRaw<'_, u32, CTRL_SPEC, bool, BitM, 20>

Bit 20 - In hardware 0x6B read operation, DIN phase apply 4 signals(4-bit-mode). 1: enable 0: disable.

pub fn wp(&mut self) -> BitWriterRaw<'_, u32, CTRL_SPEC, bool, BitM, 21>

Bit 21 - Write protect signal output when SPI is idle. 1: output high, 0: output low.

pub fn wrsr_2b(&mut self) -> BitWriterRaw<'_, u32, CTRL_SPEC, bool, BitM, 22>

Bit 22 - Two bytes data will be written to status register when it is set. 1: enable 0: disable.

pub fn fread_dio(&mut self) -> BitWriterRaw<'_, u32, CTRL_SPEC, bool, BitM, 23>

Bit 23 - In hardware 0xBB read operation, ADDR phase and DIN phase apply 2 signals(2-bit-mode). 1: enable 0: disable.

pub fn fread_qio(&mut self) -> BitWriterRaw<'_, u32, CTRL_SPEC, bool, BitM, 24>

Bit 24 - In hardware 0xEB read operation, ADDR phase and DIN phase apply 4 signals(4-bit-mode). 1: enable 0: disable.

pub unsafe fn bits(&mut self, bits: u32) -> &mut W

Writes raw bits to the register.

Methods from Deref<Target = W<CTRL_SPEC>>

pub unsafe fn bits(&mut self, bits: <REG as RegisterSpec>::Ux) -> &mut W<REG>

Writes raw bits to the register.

Safety

Read datasheet or reference manual to find what values are allowed to pass.

Trait Implementations

impl Deref for W

type Target = W<CTRL_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &<W as Deref>::Target

Dereferences the value.

impl DerefMut for W

fn deref_mut(&mut self) -> &mut <W as Deref>::Target

Mutably dereferences the value.

impl From<W<CTRL_SPEC>> for W

fn from(writer: W<CTRL_SPEC>) -> W

Converts to this type from the input type.