Struct esp32s3_hal::pac::spi1::cache_fctrl::W

pub struct W(_);
Expand description

Register CACHE_FCTRL writer

Implementations§

Bit 1 - Set this bit to enable SPI1 transfer with 32 bits address. The value of SPI_MEM_USR_ADDR_BITLEN should be 31.

Bit 3 - When SPI1 accesses to flash or Ext_RAM, set this bit to enable 2-bm in DIN phase.

Bit 4 - When SPI1 accesses to flash or Ext_RAM, set this bit to enable 2-bm in DOUT phase.

Bit 5 - When SPI1 accesses to flash or Ext_RAM, set this bit to enable 2-bm in ADDR phase.

Bit 6 - When SPI1 accesses to flash or Ext_RAM, set this bit to enable 4-bm in DIN phase.

Bit 7 - When SPI1 accesses to flash or Ext_RAM, set this bit to enable 4-bm in DOUT phase.

Bit 8 - When SPI1 accesses to flash or Ext_RAM, set this bit to enable 4-bm in ADDR phase.

Writes raw bits to the register.

Methods from Deref<Target = W<CACHE_FCTRL_SPEC>>§

Writes raw bits to the register.

Safety

Read datasheet or reference manual to find what values are allowed to pass.

Trait Implementations§

The resulting type after dereferencing.
Dereferences the value.
Mutably dereferences the value.
Converts to this type from the input type.

Auto Trait Implementations§

Blanket Implementations§

Gets the TypeId of self. Read more
Immutably borrows from an owned value. Read more
Mutably borrows from an owned value. Read more

Returns the argument unchanged.

Calls U::from(self).

That is, this conversion is whatever the implementation of From<T> for U chooses to do.

The type returned in the event of a conversion error.
Performs the conversion.
The type returned in the event of a conversion error.
Performs the conversion.