Struct esp32s3_hal::pac::spi1::cache_fctrl::R

pub struct R(_);

Register CACHE_FCTRL reader

Implementations

impl R

pub fn cache_usr_cmd_4byte(&self) -> BitReaderRaw<bool>

Bit 1 - Set this bit to enable SPI1 transfer with 32 bits address. The value of SPI_MEM_USR_ADDR_BITLEN should be 31.

pub fn fdin_dual(&self) -> BitReaderRaw<bool>

Bit 3 - When SPI1 accesses to flash or Ext_RAM, set this bit to enable 2-bm in DIN phase.

pub fn fdout_dual(&self) -> BitReaderRaw<bool>

Bit 4 - When SPI1 accesses to flash or Ext_RAM, set this bit to enable 2-bm in DOUT phase.

pub fn faddr_dual(&self) -> BitReaderRaw<bool>

Bit 5 - When SPI1 accesses to flash or Ext_RAM, set this bit to enable 2-bm in ADDR phase.

pub fn fdin_quad(&self) -> BitReaderRaw<bool>

Bit 6 - When SPI1 accesses to flash or Ext_RAM, set this bit to enable 4-bm in DIN phase.

pub fn fdout_quad(&self) -> BitReaderRaw<bool>

Bit 7 - When SPI1 accesses to flash or Ext_RAM, set this bit to enable 4-bm in DOUT phase.

pub fn faddr_quad(&self) -> BitReaderRaw<bool>

Bit 8 - When SPI1 accesses to flash or Ext_RAM, set this bit to enable 4-bm in ADDR phase.

Methods from Deref<Target = R<CACHE_FCTRL_SPEC>>

pub fn bits(&self) -> <REG as RegisterSpec>::Ux

Reads raw bits from register.

Trait Implementations

impl Deref for R

type Target = R<CACHE_FCTRL_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &<R as Deref>::Target

Dereferences the value.

impl From<R<CACHE_FCTRL_SPEC>> for R

fn from(reader: R<CACHE_FCTRL_SPEC>) -> R

Converts to this type from the input type.