Struct esp32s3_hal::pac::lcd_cam::lcd_clock::R

pub struct R(_);

Register LCD_CLOCK reader

Implementations

impl R

pub fn lcd_clkcnt_n(&self) -> FieldReaderRaw<u8, u8>

Bits 0:5 - f_LCD_PCLK = f_LCD_CLK / (reg_clkcnt_N + 1) when reg_clk_equ_sysclk is 0.

pub fn lcd_clk_equ_sysclk(&self) -> BitReaderRaw<bool>

Bit 6 - 1: f_LCD_PCLK = f_LCD_CLK. 0: f_LCD_PCLK = f_LCD_CLK / (reg_clkcnt_N + 1).

pub fn lcd_ck_idle_edge(&self) -> BitReaderRaw<bool>

Bit 7 - 1: LCD_PCLK line is high when idle 0: LCD_PCLK line is low when idle.

pub fn lcd_ck_out_edge(&self) -> BitReaderRaw<bool>

Bit 8 - 1: LCD_PCLK high in first half clock cycle. 0: LCD_PCLK low in first half clock cycle.

pub fn lcd_clkm_div_num(&self) -> FieldReaderRaw<u8, u8>

Bits 9:16 - Integral LCD clock divider value

pub fn lcd_clkm_div_b(&self) -> FieldReaderRaw<u8, u8>

Bits 17:22 - Fractional clock divider numerator value

pub fn lcd_clkm_div_a(&self) -> FieldReaderRaw<u8, u8>

Bits 23:28 - Fractional clock divider denominator value

pub fn lcd_clk_sel(&self) -> FieldReaderRaw<u8, u8>

Bits 29:30 - Select LCD module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: no clock.

pub fn clk_en(&self) -> BitReaderRaw<bool>

Bit 31 - Set this bit to enable clk gate

Methods from Deref<Target = R<LCD_CLOCK_SPEC>>

pub fn bits(&self) -> <REG as RegisterSpec>::Ux

Reads raw bits from register.

Trait Implementations

impl Deref for R

type Target = R<LCD_CLOCK_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &<R as Deref>::Target

Dereferences the value.

impl From<R<LCD_CLOCK_SPEC>> for R

fn from(reader: R<LCD_CLOCK_SPEC>) -> R

Converts to this type from the input type.