Struct esp32s3_hal::pac::extmem::dcache_autoload_ctrl::R
pub struct R(_);
Expand description
Register DCACHE_AUTOLOAD_CTRL
reader
Implementations§
§impl R
impl R
pub fn dcache_autoload_sct0_ena(&self) -> BitReaderRaw<bool>
pub fn dcache_autoload_sct0_ena(&self) -> BitReaderRaw<bool>
Bit 0 - The bits are used to enable the first section for autoload operation.
pub fn dcache_autoload_sct1_ena(&self) -> BitReaderRaw<bool>
pub fn dcache_autoload_sct1_ena(&self) -> BitReaderRaw<bool>
Bit 1 - The bits are used to enable the second section for autoload operation.
pub fn dcache_autoload_ena(&self) -> BitReaderRaw<bool>
pub fn dcache_autoload_ena(&self) -> BitReaderRaw<bool>
Bit 2 - The bit is used to enable and disable autoload operation. It is combined with dcache_autoload_done. 1: enable, 0: disable.
pub fn dcache_autoload_done(&self) -> BitReaderRaw<bool>
pub fn dcache_autoload_done(&self) -> BitReaderRaw<bool>
Bit 3 - The bit is used to indicate autoload operation is finished.
pub fn dcache_autoload_order(&self) -> BitReaderRaw<bool>
pub fn dcache_autoload_order(&self) -> BitReaderRaw<bool>
Bit 4 - The bits are used to configure the direction of autoload. 1: descending, 0: ascending.
pub fn dcache_autoload_rqst(&self) -> FieldReaderRaw<u8, u8>
pub fn dcache_autoload_rqst(&self) -> FieldReaderRaw<u8, u8>
Bits 5:6 - The bits are used to configure trigger conditions for autoload. 0/3: cache miss, 1: cache hit, 2: both cache miss and hit.
pub fn dcache_autoload_size(&self) -> FieldReaderRaw<u8, u8>
pub fn dcache_autoload_size(&self) -> FieldReaderRaw<u8, u8>
Bits 7:8 - The bits are used to configure the numbers of the cache block for the issuing autoload operation.
pub fn dcache_autoload_buffer_clear(&self) -> BitReaderRaw<bool>
pub fn dcache_autoload_buffer_clear(&self) -> BitReaderRaw<bool>
Bit 9 - The bit is used to clear autoload buffer in dcache.
Methods from Deref<Target = R<DCACHE_AUTOLOAD_CTRL_SPEC>>§
pub fn bits(&self) -> <REG as RegisterSpec>::Ux
pub fn bits(&self) -> <REG as RegisterSpec>::Ux
Reads raw bits from register.