Struct esp32s3_hal::pac::uhci0::int_st::R
pub struct R(_);
Expand description
Register INT_ST
reader
Implementations§
§impl R
impl R
pub fn rx_start_int_st(&self) -> BitReaderRaw<bool>
pub fn rx_start_int_st(&self) -> BitReaderRaw<bool>
Bit 0 - This is the masked interrupt bit for UHCI_RX_START_INT interrupt when UHCI_RX_START_INT_ENA is set to 1.
pub fn tx_start_int_st(&self) -> BitReaderRaw<bool>
pub fn tx_start_int_st(&self) -> BitReaderRaw<bool>
Bit 1 - This is the masked interrupt bit for UHCI_TX_START_INT interrupt when UHCI_TX_START_INT_ENA is set to 1.
pub fn rx_hung_int_st(&self) -> BitReaderRaw<bool>
pub fn rx_hung_int_st(&self) -> BitReaderRaw<bool>
Bit 2 - This is the masked interrupt bit for UHCI_RX_HUNG_INT interrupt when UHCI_RX_HUNG_INT_ENA is set to 1.
pub fn tx_hung_int_st(&self) -> BitReaderRaw<bool>
pub fn tx_hung_int_st(&self) -> BitReaderRaw<bool>
Bit 3 - This is the masked interrupt bit for UHCI_TX_HUNG_INT interrupt when UHCI_TX_HUNG_INT_ENA is set to 1.
pub fn send_s_reg_q_int_st(&self) -> BitReaderRaw<bool>
pub fn send_s_reg_q_int_st(&self) -> BitReaderRaw<bool>
Bit 4 - This is the masked interrupt bit for UHCI_SEND_S_REQ_Q_INT interrupt when UHCI_SEND_S_REQ_Q_INT_ENA is set to 1.
pub fn send_a_reg_q_int_st(&self) -> BitReaderRaw<bool>
pub fn send_a_reg_q_int_st(&self) -> BitReaderRaw<bool>
Bit 5 - This is the masked interrupt bit for UHCI_SEND_A_REQ_Q_INT interrupt when UHCI_SEND_A_REQ_Q_INT_ENA is set to 1.
pub fn outlink_eof_err_int_st(&self) -> BitReaderRaw<bool>
pub fn outlink_eof_err_int_st(&self) -> BitReaderRaw<bool>
Bit 6 - This is the masked interrupt bit for UHCI_OUTLINK_EOF_ERR_INT interrupt when UHCI_OUTLINK_EOF_ERR_INT_ENA is set to 1.
pub fn app_ctrl0_int_st(&self) -> BitReaderRaw<bool>
pub fn app_ctrl0_int_st(&self) -> BitReaderRaw<bool>
Bit 7 - This is the masked interrupt bit for UHCI_APP_CTRL0_INT interrupt when UHCI_APP_CTRL0_INT_ENA is set to 1.
pub fn app_ctrl1_int_st(&self) -> BitReaderRaw<bool>
pub fn app_ctrl1_int_st(&self) -> BitReaderRaw<bool>
Bit 8 - This is the masked interrupt bit for UHCI_APP_CTRL1_INT interrupt when UHCI_APP_CTRL1_INT_ENA is set to 1.
Methods from Deref<Target = R<INT_ST_SPEC>>§
pub fn bits(&self) -> <REG as RegisterSpec>::Ux
pub fn bits(&self) -> <REG as RegisterSpec>::Ux
Reads raw bits from register.