Struct esp32s3_hal::pac::spi2::din_mode::W

pub struct W(_);

Register DIN_MODE writer

Implementations

impl W

pub fn din0_mode(
    &mut self
) -> FieldWriterRaw<'_, u32, DIN_MODE_SPEC, u8, u8, Unsafe, 2, 0>

Bits 0:1 - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.

pub fn din1_mode(
    &mut self
) -> FieldWriterRaw<'_, u32, DIN_MODE_SPEC, u8, u8, Unsafe, 2, 2>

Bits 2:3 - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.

pub fn din2_mode(
    &mut self
) -> FieldWriterRaw<'_, u32, DIN_MODE_SPEC, u8, u8, Unsafe, 2, 4>

Bits 4:5 - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.

pub fn din3_mode(
    &mut self
) -> FieldWriterRaw<'_, u32, DIN_MODE_SPEC, u8, u8, Unsafe, 2, 6>

Bits 6:7 - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.

pub fn din4_mode(
    &mut self
) -> FieldWriterRaw<'_, u32, DIN_MODE_SPEC, u8, u8, Unsafe, 2, 8>

Bits 8:9 - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.

pub fn din5_mode(
    &mut self
) -> FieldWriterRaw<'_, u32, DIN_MODE_SPEC, u8, u8, Unsafe, 2, 10>

Bits 10:11 - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.

pub fn din6_mode(
    &mut self
) -> FieldWriterRaw<'_, u32, DIN_MODE_SPEC, u8, u8, Unsafe, 2, 12>

Bits 12:13 - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.

pub fn din7_mode(
    &mut self
) -> FieldWriterRaw<'_, u32, DIN_MODE_SPEC, u8, u8, Unsafe, 2, 14>

Bits 14:15 - the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.

pub fn timing_hclk_active(
    &mut self
) -> BitWriterRaw<'_, u32, DIN_MODE_SPEC, bool, BitM, 16>

Bit 16 - 1:enable hclk in SPI input timing module. 0: disable it. Can be configured in CONF state.

pub unsafe fn bits(&mut self, bits: u32) -> &mut W

Writes raw bits to the register.

Methods from Deref<Target = W<DIN_MODE_SPEC>>

pub unsafe fn bits(&mut self, bits: <REG as RegisterSpec>::Ux) -> &mut W<REG>

Writes raw bits to the register.

Safety

Read datasheet or reference manual to find what values are allowed to pass.

Trait Implementations

impl Deref for W

type Target = W<DIN_MODE_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &<W as Deref>::Target

Dereferences the value.

impl DerefMut for W

fn deref_mut(&mut self) -> &mut <W as Deref>::Target

Mutably dereferences the value.

impl From<W<DIN_MODE_SPEC>> for W

fn from(writer: W<DIN_MODE_SPEC>) -> W

Converts to this type from the input type.