Struct esp32s3_hal::pac::spi1::ddr::W

pub struct W(_);

Register DDR writer

Implementations

impl W

pub fn spi_fmem_ddr_en(
    &mut self
) -> BitWriterRaw<'_, u32, DDR_SPEC, bool, BitM, 0>

Bit 0 - 1: in DDR mode, 0: in SDR mode.

pub fn spi_fmem_var_dummy(
    &mut self
) -> BitWriterRaw<'_, u32, DDR_SPEC, bool, BitM, 1>

Bit 1 - Set the bit to enable variable dummy cycle in DDRmode.

pub fn spi_fmem_ddr_rdat_swp(
    &mut self
) -> BitWriterRaw<'_, u32, DDR_SPEC, bool, BitM, 2>

Bit 2 - Set the bit to reorder RX data of the word in DDR mode.

pub fn spi_fmem_ddr_wdat_swp(
    &mut self
) -> BitWriterRaw<'_, u32, DDR_SPEC, bool, BitM, 3>

Bit 3 - Set the bit to reorder TX data of the word in DDR mode.

pub fn spi_fmem_ddr_cmd_dis(
    &mut self
) -> BitWriterRaw<'_, u32, DDR_SPEC, bool, BitM, 4>

Bit 4 - the bit is used to disable dual edge in command phase when DDR mode.

pub fn spi_fmem_outminbytelen(
    &mut self
) -> FieldWriterRaw<'_, u32, DDR_SPEC, u8, u8, Unsafe, 7, 5>

Bits 5:11 - It is the minimum output data length in the panda device.

pub fn spi_fmem_usr_ddr_dqs_thd(
    &mut self
) -> FieldWriterRaw<'_, u32, DDR_SPEC, u8, u8, Unsafe, 7, 14>

Bits 14:20 - The delay number of data strobe which from memory based on SPI_CLK.

pub fn spi_fmem_ddr_dqs_loop(
    &mut self
) -> BitWriterRaw<'_, u32, DDR_SPEC, bool, BitM, 21>

Bit 21 - 1: Use internal signal as data strobe, the strobe can not be delayed by input timing module. 0: Use input SPI_DQS signal from PAD as data strobe, the strobe can be delayed by input timing module

pub fn spi_fmem_ddr_dqs_loop_mode(
    &mut self
) -> BitWriterRaw<'_, u32, DDR_SPEC, bool, BitM, 22>

Bit 22 - When SPI_FMEM_DDR_DQS_LOOP and SPI_FMEM_DDR_EN are set, 1: Use internal SPI_CLK as data strobe. 0: Use internal ~SPI_CLK as data strobe. Otherwise this bit is not active.

pub fn spi_fmem_clk_diff_en(
    &mut self
) -> BitWriterRaw<'_, u32, DDR_SPEC, bool, BitM, 24>

Bit 24 - Set this bit to enable the differential SPI_CLK#.

pub fn spi_fmem_hyperbus_mode(
    &mut self
) -> BitWriterRaw<'_, u32, DDR_SPEC, bool, BitM, 25>

Bit 25 - Set this bit to enable the SPI HyperBus mode.

pub fn spi_fmem_dqs_ca_in(
    &mut self
) -> BitWriterRaw<'_, u32, DDR_SPEC, bool, BitM, 26>

Bit 26 - Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR.

pub fn spi_fmem_hyperbus_dummy_2x(
    &mut self
) -> BitWriterRaw<'_, u32, DDR_SPEC, bool, BitM, 27>

Bit 27 - Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 accesses flash or SPI1 accesses flash or sram.

pub fn spi_fmem_clk_diff_inv(
    &mut self
) -> BitWriterRaw<'_, u32, DDR_SPEC, bool, BitM, 28>

Bit 28 - Set this bit to invert SPI_DIFF when accesses to flash. .

pub fn spi_fmem_octa_ram_addr(
    &mut self
) -> BitWriterRaw<'_, u32, DDR_SPEC, bool, BitM, 29>

Bit 29 - Set this bit to enable octa_ram address out when accesses to flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6’d0, spi_usr_addr_value[3:1], 1’b0}.

pub fn spi_fmem_hyperbus_ca(
    &mut self
) -> BitWriterRaw<'_, u32, DDR_SPEC, bool, BitM, 30>

Bit 30 - Set this bit to enable HyperRAM address out when accesses to flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13’d0, spi_usr_addr_value[3:1]}.

pub unsafe fn bits(&mut self, bits: u32) -> &mut W

Writes raw bits to the register.

Methods from Deref<Target = W<DDR_SPEC>>

pub unsafe fn bits(&mut self, bits: <REG as RegisterSpec>::Ux) -> &mut W<REG>

Writes raw bits to the register.

Safety

Read datasheet or reference manual to find what values are allowed to pass.

Trait Implementations

impl Deref for W

type Target = W<DDR_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &<W as Deref>::Target

Dereferences the value.

impl DerefMut for W

fn deref_mut(&mut self) -> &mut <W as Deref>::Target

Mutably dereferences the value.

impl From<W<DDR_SPEC>> for W

fn from(writer: W<DDR_SPEC>) -> W

Converts to this type from the input type.