Struct esp32s3_hal::pac::spi1::ddr::R
pub struct R(_);Expand description
Register DDR reader
Implementations§
§impl R
impl R
pub fn spi_fmem_ddr_en(&self) -> BitReaderRaw<bool>
pub fn spi_fmem_ddr_en(&self) -> BitReaderRaw<bool>
Bit 0 - 1: in DDR mode, 0: in SDR mode.
pub fn spi_fmem_var_dummy(&self) -> BitReaderRaw<bool>
pub fn spi_fmem_var_dummy(&self) -> BitReaderRaw<bool>
Bit 1 - Set the bit to enable variable dummy cycle in DDRmode.
pub fn spi_fmem_ddr_rdat_swp(&self) -> BitReaderRaw<bool>
pub fn spi_fmem_ddr_rdat_swp(&self) -> BitReaderRaw<bool>
Bit 2 - Set the bit to reorder RX data of the word in DDR mode.
pub fn spi_fmem_ddr_wdat_swp(&self) -> BitReaderRaw<bool>
pub fn spi_fmem_ddr_wdat_swp(&self) -> BitReaderRaw<bool>
Bit 3 - Set the bit to reorder TX data of the word in DDR mode.
pub fn spi_fmem_ddr_cmd_dis(&self) -> BitReaderRaw<bool>
pub fn spi_fmem_ddr_cmd_dis(&self) -> BitReaderRaw<bool>
Bit 4 - the bit is used to disable dual edge in command phase when DDR mode.
pub fn spi_fmem_outminbytelen(&self) -> FieldReaderRaw<u8, u8>
pub fn spi_fmem_outminbytelen(&self) -> FieldReaderRaw<u8, u8>
Bits 5:11 - It is the minimum output data length in the panda device.
pub fn spi_fmem_usr_ddr_dqs_thd(&self) -> FieldReaderRaw<u8, u8>
pub fn spi_fmem_usr_ddr_dqs_thd(&self) -> FieldReaderRaw<u8, u8>
Bits 14:20 - The delay number of data strobe which from memory based on SPI_CLK.
pub fn spi_fmem_ddr_dqs_loop(&self) -> BitReaderRaw<bool>
pub fn spi_fmem_ddr_dqs_loop(&self) -> BitReaderRaw<bool>
Bit 21 - 1: Use internal signal as data strobe, the strobe can not be delayed by input timing module. 0: Use input SPI_DQS signal from PAD as data strobe, the strobe can be delayed by input timing module
pub fn spi_fmem_ddr_dqs_loop_mode(&self) -> BitReaderRaw<bool>
pub fn spi_fmem_ddr_dqs_loop_mode(&self) -> BitReaderRaw<bool>
Bit 22 - When SPI_FMEM_DDR_DQS_LOOP and SPI_FMEM_DDR_EN are set, 1: Use internal SPI_CLK as data strobe. 0: Use internal ~SPI_CLK as data strobe. Otherwise this bit is not active.
pub fn spi_fmem_clk_diff_en(&self) -> BitReaderRaw<bool>
pub fn spi_fmem_clk_diff_en(&self) -> BitReaderRaw<bool>
Bit 24 - Set this bit to enable the differential SPI_CLK#.
pub fn spi_fmem_hyperbus_mode(&self) -> BitReaderRaw<bool>
pub fn spi_fmem_hyperbus_mode(&self) -> BitReaderRaw<bool>
Bit 25 - Set this bit to enable the SPI HyperBus mode.
pub fn spi_fmem_dqs_ca_in(&self) -> BitReaderRaw<bool>
pub fn spi_fmem_dqs_ca_in(&self) -> BitReaderRaw<bool>
Bit 26 - Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR.
pub fn spi_fmem_hyperbus_dummy_2x(&self) -> BitReaderRaw<bool>
pub fn spi_fmem_hyperbus_dummy_2x(&self) -> BitReaderRaw<bool>
Bit 27 - Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 accesses flash or SPI1 accesses flash or sram.
pub fn spi_fmem_clk_diff_inv(&self) -> BitReaderRaw<bool>
pub fn spi_fmem_clk_diff_inv(&self) -> BitReaderRaw<bool>
Bit 28 - Set this bit to invert SPI_DIFF when accesses to flash. .
pub fn spi_fmem_octa_ram_addr(&self) -> BitReaderRaw<bool>
pub fn spi_fmem_octa_ram_addr(&self) -> BitReaderRaw<bool>
Bit 29 - Set this bit to enable octa_ram address out when accesses to flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6’d0, spi_usr_addr_value[3:1], 1’b0}.
pub fn spi_fmem_hyperbus_ca(&self) -> BitReaderRaw<bool>
pub fn spi_fmem_hyperbus_ca(&self) -> BitReaderRaw<bool>
Bit 30 - Set this bit to enable HyperRAM address out when accesses to flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13’d0, spi_usr_addr_value[3:1]}.
Methods from Deref<Target = R<DDR_SPEC>>§
pub fn bits(&self) -> <REG as RegisterSpec>::Ux
pub fn bits(&self) -> <REG as RegisterSpec>::Ux
Reads raw bits from register.