Struct esp32s3_hal::pac::spi0::timing_cali::R

pub struct R(_);

Register TIMING_CALI reader

Implementations

impl R

pub fn timing_clk_ena(&self) -> BitReaderRaw<bool>

Bit 0 - Set this bit to power on HCLK. When PLL is powered on, the frequency of HCLK equals to that of PLL. Otherwise, the frequency equals to that of XTAL.

pub fn timing_cali(&self) -> BitReaderRaw<bool>

Bit 1 - Set this bit to add extra SPI_CLK cycles in DUMMY phase for all reading operations.

pub fn extra_dummy_cyclelen(&self) -> FieldReaderRaw<u8, u8>

Bits 2:4 - Extra SPI_CLK cycles added in DUMMY phase for timing compensation, when SPI0 accesses to flash. Active when SPI_MEM_TIMING_CALI bit is set.

Methods from Deref<Target = R<TIMING_CALI_SPEC>>

pub fn bits(&self) -> <REG as RegisterSpec>::Ux

Reads raw bits from register.

Trait Implementations

impl Deref for R

type Target = R<TIMING_CALI_SPEC>

The resulting type after dereferencing.

fn deref(&self) -> &<R as Deref>::Target

Dereferences the value.

impl From<R<TIMING_CALI_SPEC>> for R

fn from(reader: R<TIMING_CALI_SPEC>) -> R

Converts to this type from the input type.